Loading qcom/sdxlemur-coresight.dtsi +6 −2 Original line number Diff line number Diff line Loading @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; coresight-ctis = <&cti0 &cti6>; coresight-ctis = <&cti0_swao &cti3_swao>; cti-reset-trig-num = <0>; cti-flush-trig-num = <1>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading @@ -147,7 +149,9 @@ arm,scatter-gather; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti6>; coresight-ctis = <&cti0 &cti3_swao>; cti-reset-trig-num = <0>; cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; Loading qcom/sdxlemur.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -946,6 +946,7 @@ #include "sdxlemur-pinctrl.dtsi" #include "sdxlemur-regulators.dtsi" #include "sdxlemur-coresight.dtsi" #include "msm-arm-smmu-sdxlemur.dtsi" #include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi" Loading Loading
qcom/sdxlemur-coresight.dtsi +6 −2 Original line number Diff line number Diff line Loading @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; coresight-ctis = <&cti0 &cti6>; coresight-ctis = <&cti0_swao &cti3_swao>; cti-reset-trig-num = <0>; cti-flush-trig-num = <1>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; Loading Loading @@ -147,7 +149,9 @@ arm,scatter-gather; coresight-name = "coresight-tmc-etr"; coresight-ctis = <&cti0 &cti6>; coresight-ctis = <&cti0 &cti3_swao>; cti-reset-trig-num = <0>; cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; Loading
qcom/sdxlemur.dtsi +1 −0 Original line number Diff line number Diff line Loading @@ -946,6 +946,7 @@ #include "sdxlemur-pinctrl.dtsi" #include "sdxlemur-regulators.dtsi" #include "sdxlemur-coresight.dtsi" #include "msm-arm-smmu-sdxlemur.dtsi" #include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi" Loading