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Commit 613398d2 authored by Ashok Vuyyuru's avatar Ashok Vuyyuru
Browse files

msm: ipa3: Changes to read the halt command return code after some delay 



In some cases for updating the return code in SCRATCH register taking
time after raising the global interrupt. Adding changes to wait for
some time read the SCRATCH register again and also printing the
test bus registers and Q6 channel state in failed scenario.

Change-Id: I4112a2290739daa79629f718d9725258518aba4c
Signed-off-by: default avatarAshok Vuyyuru <avuyyuru@codeaurora.org>
parent e74ef506

drivers/platform/msm/gsi/gsi.c

+50 −2
Original line number Diff line number Diff line
@@ -4490,6 +4490,45 @@ void gsi_get_inst_ram_offset_and_size(unsigned long *base_offset, 
}

EXPORT_SYMBOL(gsi_get_inst_ram_offset_and_size);



/*

 * Dumping the Debug registers for halt issue debugging.

 */

static void gsi_dump_halt_debug_reg(unsigned int chan_idx, unsigned int ee)

{

	uint32_t val;

	enum gsi_chan_state curr_state = GSI_CHAN_STATE_NOT_ALLOCATED;



	GSIERR("DEBUG_PC_FOR_DEBUG = 0x%x\n", gsi_readl(gsi_ctx->base +

			GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS));



	GSIERR("GSI_DEBUG_BUSY_REG 0x%x\n",

		gsi_readl(gsi_ctx->base + GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS));



	GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_EN_OFFS = 0x%x\n",

		gsi_readl(gsi_ctx->base +

			GSI_EE_n_CNTXT_GLOB_IRQ_EN_OFFS(gsi_ctx->per.ee)));



	GSIERR("GSI_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS IRQ type = 0x%x\n",

		gsi_readl(gsi_ctx->base +

			GSI_EE_n_CNTXT_GLOB_IRQ_STTS_OFFS(gsi_ctx->per.ee)));



	GSIERR("GSI_EE_n_CNTXT_SCRATCH_0_OFFS = 0x%x\n",

		gsi_readl(gsi_ctx->base +

			GSI_EE_n_CNTXT_SCRATCH_0_OFFS(gsi_ctx->per.ee)));



	if (gsi_ctx->per.ver >= GSI_VER_2_9)

		GSIERR("GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS = 0x%x\n",

			gsi_readl(gsi_ctx->base +

			GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(chan_idx, ee)));



	val = gsi_readl(gsi_ctx->base +

			GSI_EE_n_GSI_CH_k_CNTXT_0_OFFS(chan_idx, ee));

	curr_state = (val &

			GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_BMSK) >>

		GSI_EE_n_GSI_CH_k_CNTXT_0_CHSTATE_SHFT;

	GSIERR("Q6 channel [%d] state =  %d\n", chan_idx, curr_state);

}



int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code)

{

	enum gsi_generic_ee_cmd_opcode op = GSI_GEN_EE_CMD_HALT_CHANNEL;
@@ -4544,9 +4583,18 @@ int gsi_halt_channel_ee(unsigned int chan_idx, unsigned int ee, int *code) 
	}

	if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) {

		GSIERR("No response received\n");

		gsi_dump_halt_debug_reg(chan_idx, ee);

		usleep_range(GSI_RESET_WA_MIN_SLEEP, GSI_RESET_WA_MAX_SLEEP);

		GSIERR("Reading after usleep scratch 0 reg\n");

		gsi_ctx->scratch.word0.val = gsi_readl(gsi_ctx->base +

				GSI_EE_n_CNTXT_SCRATCH_0_OFFS(gsi_ctx->per.ee));

		if (gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code == 0) {

			GSIERR("No response received second attempt\n");

			gsi_dump_halt_debug_reg(chan_idx, ee);

			res = -GSI_STATUS_ERROR;

			goto free_lock;

		}

	}



	res = GSI_STATUS_SUCCESS;

	*code = gsi_ctx->scratch.word0.s.generic_ee_cmd_return_code;

drivers/platform/msm/gsi/gsi_reg_v1.h

+9 −0
Original line number Diff line number Diff line
@@ -1242,4 +1242,13 @@ 
#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_THREE_N_HALF_KB_FVAL 0x4

#define GSI_V2_7_EE_n_GSI_HW_PARAM_2_GSI_IRAM_SIZE_FOUR_KB_FVAL 0x5



#define GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS \

	(GSI_GSI_REG_BASE_OFFS + 0x00001048)



#define GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS \

	(GSI_GSI_REG_BASE_OFFS + 0x00001010)



#define GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(k, n) \

	(GSI_GSI_REG_BASE_OFFS + 0x0000f040 + 0x4000 * (n) + 0x80 * (k))



#endif /* __GSI_REG_V1_H__ */

drivers/platform/msm/gsi/gsi_reg_v2.h

+9 −0
Original line number Diff line number Diff line
@@ -1252,4 +1252,13 @@ 
#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_RMSK 0xffffffff

#define GSI_GSI_MCS_PROFILING_MCS_IDLE_CNT_MSB_SHFT 0x0



#define GSI_EE_n_GSI_DEBUG_PC_FOR_DEBUG_OFFS \

	(GSI_GSI_REG_BASE_OFFS + 0x00001048)



#define GSI_EE_n_GSI_DEBUG_BUSY_REG_OFFS \

	(GSI_GSI_REG_BASE_OFFS + 0x00001010)



#define GSI_EE_n_GSI_CH_k_SCRATCH_4_OFFS(k, n) \

	(GSI_GSI_REG_BASE_OFFS + 0x0000f040 + 0x4000 * (n) + 0x80 * (k))



#endif /* __GSI_REG_V2_H__ */