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Commit 60e5ffe3 authored by Rodrigo Vivi's avatar Rodrigo Vivi
Browse files

drm/i915: Add PSR main link standby support back 



Link standby support has been deprecated with 'commit 89251b17
("drm/i915: PSR: deprecate link_standby support for core platforms.")'

The reason for that is that main link in full off offers more power
savings and on HSW and BDW implementations on source side had known
bugs with link standby.

However that same HSD report only mentions BDW and HSW and tells that
a fix was going to new platforms. Since on Skylake link standby
didn't cause the bad blank flickering screens seen on HSW and BDW
let's respect VBT again for this and future platforms.

Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
parent dc9b5a0c

drivers/gpu/drm/i915/i915_debugfs.c

+4 −0
Original line number Diff line number Diff line
@@ -2583,6 +2583,10 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) 
				enabled = true;

		}

	}



	seq_printf(m, "Main link in standby mode: %s\n",

		   yesno(dev_priv->psr.link_standby));



	seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));



	if (!HAS_DDI(dev))

drivers/gpu/drm/i915/i915_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -1007,6 +1007,7 @@ struct i915_psr { 
	unsigned busy_frontbuffer_bits;

	bool psr2_support;

	bool aux_frame_sync;

	bool link_standby;

};



enum intel_pch {

drivers/gpu/drm/i915/intel_psr.c

+19 −7
Original line number Diff line number Diff line
@@ -225,7 +225,12 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) 
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));

	}



	drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);

	if (dev_priv->psr.link_standby)

		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,

				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);

	else

		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,

				   DP_PSR_ENABLE);

}



static void vlv_psr_enable_source(struct intel_dp *intel_dp)
@@ -280,6 +285,9 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp) 
	if (IS_HASWELL(dev))

		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;



	if (dev_priv->psr.link_standby)

		val |= EDP_PSR_LINK_STANDBY;



	I915_WRITE(EDP_PSR_CTL, val |

		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |

		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
@@ -334,12 +342,6 @@ static bool intel_psr_match_conditions(struct intel_dp *intel_dp) 
		return false;

	}



	if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&

	    dev_priv->vbt.psr.full_link) {

		DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");

		return false;

	}



	dev_priv->psr.source_ok = true;

	return true;

}
@@ -770,6 +772,16 @@ void intel_psr_init(struct drm_device *dev) 
	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?

		HSW_EDP_PSR_BASE : BDW_EDP_PSR_BASE;



	if (IS_HASWELL(dev) || IS_BROADWELL(dev))

		/* HSW and BDW require workarounds that we don't implement. */

		dev_priv->psr.link_standby = false;

	else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))

		/* On VLV and CHV only standby mode is supported. */

		dev_priv->psr.link_standby = true;

	else

		/* For new platforms let's respect VBT back again */

		dev_priv->psr.link_standby = dev_priv->vbt.psr.full_link;



	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);

	mutex_init(&dev_priv->psr.lock);

}