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Commit 6078ab19 authored by Rahul Lakkireddy's avatar Rahul Lakkireddy Committed by David S. Miller
Browse files

cxgb4: collect PCIe configuration logs 



Signed-off-by: default avatarRahul Lakkireddy <rahul.lakkireddy@chelsio.com>
Signed-off-by: default avatarGanesh Goudar <ganeshgr@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 736c3b94

drivers/net/ethernet/chelsio/cxgb4/cudbg_entity.h

+19 −0
Original line number Diff line number Diff line
@@ -375,6 +375,25 @@ static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = { 
	{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */

};



#define CUDBG_NUM_PCIE_CONFIG_REGS 0x61



static const u32 t5_pcie_config_array[][2] = {

	{0x0, 0x34},

	{0x3c, 0x40},

	{0x50, 0x64},

	{0x70, 0x80},

	{0x94, 0xa0},

	{0xb0, 0xb8},

	{0xd0, 0xd4},

	{0x100, 0x128},

	{0x140, 0x148},

	{0x150, 0x164},

	{0x170, 0x178},

	{0x180, 0x194},

	{0x1a0, 0x1b8},

	{0x1c0, 0x208},

};



static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {

	{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */

	{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */

drivers/net/ethernet/chelsio/cxgb4/cudbg_if.h

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ enum cudbg_dbg_entity_type { 
	CUDBG_PCIE_INDIRECT = 50,

	CUDBG_PM_INDIRECT = 51,

	CUDBG_TID_INFO = 54,

	CUDBG_PCIE_CONFIG = 55,

	CUDBG_DUMP_CONTEXT = 56,

	CUDBG_MPS_TCAM = 57,

	CUDBG_VPD_DATA = 58,

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.c

+27 −0
Original line number Diff line number Diff line
@@ -1594,6 +1594,33 @@ int cudbg_collect_tid(struct cudbg_init *pdbg_init, 
	return rc;

}



int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init,

			      struct cudbg_buffer *dbg_buff,

			      struct cudbg_error *cudbg_err)

{

	struct adapter *padap = pdbg_init->adap;

	struct cudbg_buffer temp_buff = { 0 };

	u32 size, *value, j;

	int i, rc, n;



	size = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;

	n = sizeof(t5_pcie_config_array) / (2 * sizeof(u32));

	rc = cudbg_get_buff(dbg_buff, size, &temp_buff);

	if (rc)

		return rc;



	value = (u32 *)temp_buff.data;

	for (i = 0; i < n; i++) {

		for (j = t5_pcie_config_array[i][0];

		     j <= t5_pcie_config_array[i][1]; j += 4) {

			t4_hw_pci_read_cfg4(padap, j, value);

			value++;

		}

	}

	cudbg_write_and_release_buff(&temp_buff, dbg_buff);

	return rc;

}



static int cudbg_sge_ctxt_check_valid(u32 *buf, int type)

{

	int index, bit, bit_pos = 0;

drivers/net/ethernet/chelsio/cxgb4/cudbg_lib.h

+3 −0
Original line number Diff line number Diff line
@@ -132,6 +132,9 @@ int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init, 
int cudbg_collect_tid(struct cudbg_init *pdbg_init,

		      struct cudbg_buffer *dbg_buff,

		      struct cudbg_error *cudbg_err);

int cudbg_collect_pcie_config(struct cudbg_init *pdbg_init,

			      struct cudbg_buffer *dbg_buff,

			      struct cudbg_error *cudbg_err);

int cudbg_collect_dump_context(struct cudbg_init *pdbg_init,

			       struct cudbg_buffer *dbg_buff,

			       struct cudbg_error *cudbg_err);

drivers/net/ethernet/chelsio/cxgb4/cxgb4_cudbg.c

+4 −0
Original line number Diff line number Diff line
@@ -63,6 +63,7 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = { 
	{ CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect },

	{ CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect },

	{ CUDBG_TID_INFO, cudbg_collect_tid },

	{ CUDBG_PCIE_CONFIG, cudbg_collect_pcie_config },

	{ CUDBG_DUMP_CONTEXT, cudbg_collect_dump_context },

	{ CUDBG_MPS_TCAM, cudbg_collect_mps_tcam },

	{ CUDBG_VPD_DATA, cudbg_collect_vpd_data },
@@ -241,6 +242,9 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity) 
	case CUDBG_TID_INFO:

		len = sizeof(struct cudbg_tid_info_region_rev1);

		break;

	case CUDBG_PCIE_CONFIG:

		len = sizeof(u32) * CUDBG_NUM_PCIE_CONFIG_REGS;

		break;

	case CUDBG_DUMP_CONTEXT:

		len = cudbg_dump_context_size(adap);

		break;