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Commit 60133f5e authored by Steve Cohen's avatar Steve Cohen
Browse files

disp: msm: sde: pre-downscale support for inline rotation v2 



Add support for enabling pre-downscale block to increase the
maximum downscale capability for true inline rotation use cases.

Change-Id: Ifa544bb0ae69439abef4bd427134290090fe7230
Signed-off-by: default avatarSteve Cohen <cohens@codeaurora.org>
parent 5a55e2d1

msm/sde/sde_hw_catalog.c

+29 −17
Original line number Diff line number Diff line
@@ -69,9 +69,12 @@ 
#define MAX_DOWNSCALE_RATIO		4

#define SSPP_UNITY_SCALE		1



#define MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR	11

#define MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR	5

#define MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT	4

#define MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_NUMERATOR	11

#define MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_DENOMINATOR	5

#define MAX_DOWNSCALE_RATIO_INROT_PD_RT_NUMERATOR	4

#define MAX_DOWNSCALE_RATIO_INROT_PD_RT_DENOMINATOR	1

#define MAX_DOWNSCALE_RATIO_INROT_NRT_DEFAULT		4



#define MAX_PRE_ROT_HEIGHT_INLINE_ROT_DEFAULT	1088



#define MAX_HORZ_DECIMATION		4
@@ -1255,8 +1258,10 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 


	sblk->format_list = sde_cfg->vig_formats;

	sblk->virt_format_list = sde_cfg->virt_vig_formats;

	if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev)) {

		set_bit(SDE_SSPP_TRUE_INLINE_ROT_V1, &sspp->features);

	if (IS_SDE_INLINE_ROT_REV_100(sde_cfg->true_inline_rot_rev) ||

			IS_SDE_INLINE_ROT_REV_200(

			sde_cfg->true_inline_rot_rev)) {

		set_bit(SDE_SSPP_TRUE_INLINE_ROT, &sspp->features);

		sblk->in_rot_format_list = sde_cfg->inline_rot_formats;

		sblk->in_rot_maxdwnscale_rt_num =

			sde_cfg->true_inline_dwnscale_rt_num;
@@ -1274,6 +1279,14 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
			sde_cfg->true_inline_prefill_lines;

	}



	if (IS_SDE_INLINE_ROT_REV_200(sde_cfg->true_inline_rot_rev)) {

		set_bit(SDE_SSPP_PREDOWNSCALE, &sspp->features);

		sblk->in_rot_minpredwnscale_num =

				MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_NUMERATOR;

		sblk->in_rot_minpredwnscale_denom =

				MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_DENOMINATOR;

	}



	if (sde_cfg->sc_cfg.has_sys_cache) {

		set_bit(SDE_PERF_SSPP_SYS_CACHE, &sspp->perf_features);

		sblk->llcc_scid = sde_cfg->sc_cfg.llcc_scid;
@@ -2311,8 +2324,7 @@ static int sde_rot_parse_dt(struct device_node *np, 
	if (rc) {

		/*

		 * This is not a fatal error, system cache can be disabled

		 * in device tree, anyways recommendation is to have it

		 * enabled, so print an error but don't fail

		 * in device tree

		 */

		SDE_DEBUG("sys cache will be disabled rc:%d\n", rc);

		rc = 0;
@@ -4310,11 +4322,11 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_vig_p010 = true;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;

		sde_cfg->true_inline_dwnscale_rt_num =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;

			MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_NUMERATOR;

		sde_cfg->true_inline_dwnscale_rt_denom =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;

			MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_DENOMINATOR;

		sde_cfg->true_inline_dwnscale_nrt =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;

			MAX_DOWNSCALE_RATIO_INROT_NRT_DEFAULT;

		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;
@@ -4341,11 +4353,11 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_vig_p010 = true;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;

		sde_cfg->true_inline_dwnscale_rt_num =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;

			MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_NUMERATOR;

		sde_cfg->true_inline_dwnscale_rt_denom =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;

			MAX_DOWNSCALE_RATIO_INROT_NOPD_RT_DENOMINATOR;

		sde_cfg->true_inline_dwnscale_nrt =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;

			MAX_DOWNSCALE_RATIO_INROT_NRT_DEFAULT;

		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;
@@ -4395,13 +4407,13 @@ static int _sde_hardware_pre_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->has_hdr_plus = true;

		set_bit(SDE_MDP_DHDR_MEMPOOL, &sde_cfg->mdp[0].features);

		sde_cfg->has_vig_p010 = true;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_1_0_0;

		sde_cfg->true_inline_rot_rev = SDE_INLINE_ROT_VERSION_2_0_0;

		sde_cfg->true_inline_dwnscale_rt_num =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_NUMERATOR;

				MAX_DOWNSCALE_RATIO_INROT_PD_RT_NUMERATOR;

		sde_cfg->true_inline_dwnscale_rt_denom =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_RT_DENOMINATOR;

				MAX_DOWNSCALE_RATIO_INROT_PD_RT_DENOMINATOR;

		sde_cfg->true_inline_dwnscale_nrt =

			MAX_DOWNSCALE_RATIO_INLINE_ROT_NRT_DEFAULT;

				MAX_DOWNSCALE_RATIO_INROT_NRT_DEFAULT;

		sde_cfg->true_inline_prefill_fudge_lines = 2;

		sde_cfg->true_inline_prefill_lines_nv12 = 32;

		sde_cfg->true_inline_prefill_lines = 48;

msm/sde/sde_hw_catalog.h

+8 −2
Original line number Diff line number Diff line
@@ -216,7 +216,8 @@ enum { 
 * @SDE_SSPP_SEC_UI_ALLOWED   Allows secure-ui layers

 * @SDE_SSPP_BLOCK_SEC_UI    Blocks secure-ui layers

 * @SDE_SSPP_SCALER_QSEED3LITE Qseed3lite algorithm support

 * @SDE_SSPP_TRUE_INLINE_ROT_V1, Support of SSPP true inline rotation v1

 * @SDE_SSPP_TRUE_INLINE_ROT Support of SSPP true inline rotation v1

 * @SDE_SSPP_PREDOWNSCALE    Support pre-downscale X-direction by 2 for inline

 * @SDE_SSPP_INLINE_CONST_CLR Inline rotation requires const clr disabled

 * @SDE_SSPP_MAX             maximum value

 */
@@ -245,7 +246,8 @@ enum { 
	SDE_SSPP_SEC_UI_ALLOWED,

	SDE_SSPP_BLOCK_SEC_UI,

	SDE_SSPP_SCALER_QSEED3LITE,

	SDE_SSPP_TRUE_INLINE_ROT_V1,

	SDE_SSPP_TRUE_INLINE_ROT,

	SDE_SSPP_PREDOWNSCALE,

	SDE_SSPP_INLINE_CONST_CLR,

	SDE_SSPP_MAX

};
@@ -622,6 +624,8 @@ struct sde_qos_lut_tbl { 
 * @in_rot_maxdwnscale_rt_denom: max downscale ratio for inline rotation

 *                                 rt clients - denominator

 * @in_rot_maxdwnscale_nrt: max downscale ratio for inline rotation nrt clients

 * @in_rot_minpredwnscale_num: min downscale ratio to enable pre-downscale

 * @in_rot_minpredwnscale_denom: min downscale ratio to enable pre-downscale

 * @in_rot_maxheight: max pre rotated height for inline rotation

 * @in_rot_prefill_fudge_lines: prefill fudge lines for inline rotation

 * @in_rot_prefill_lines_mv12: prefill lines for nv12 format inline rotation
@@ -661,6 +665,8 @@ struct sde_sspp_sub_blks { 
	u32 in_rot_maxdwnscale_rt_num;

	u32 in_rot_maxdwnscale_rt_denom;

	u32 in_rot_maxdwnscale_nrt;

	u32 in_rot_minpredwnscale_num;

	u32 in_rot_minpredwnscale_denom;

	u32 in_rot_maxheight;

	u32 in_rot_prefill_fudge_lines;

	u32 in_rot_prefill_lines_nv12;

msm/sde/sde_hw_sspp.c

+21 −1
Original line number Diff line number Diff line
@@ -67,7 +67,8 @@ 
#define SSPP_SRC_CONSTANT_COLOR            0x3c

#define SSPP_EXCL_REC_CTL                  0x40

#define SSPP_UBWC_STATIC_CTRL              0x44

#define SSPP_FETCH_CONFIG                  0x048

#define SSPP_FETCH_CONFIG                  0x48

#define SSPP_PRE_DOWN_SCALE                0x50

#define SSPP_DANGER_LUT                    0x60

#define SSPP_SAFE_LUT                      0x64

#define SSPP_CREQ_LUT                      0x68
@@ -596,6 +597,22 @@ static void _sde_hw_sspp_setup_scaler3(struct sde_hw_pipe *ctx, 
		ctx->cap->sblk->scaler_blk.version, idx, sspp->layout.format);

}



static void sde_hw_sspp_setup_pre_downscale(struct sde_hw_pipe *ctx,

		struct sde_hw_inline_pre_downscale_cfg *pre_down)

{

	u32 idx, val;



	if (!ctx || !pre_down || _sspp_subblk_offset(ctx, SDE_SSPP_SRC, &idx))

		return;



	val = pre_down->pre_downscale_x_0 |

			(pre_down->pre_downscale_x_1 << 4) |

			(pre_down->pre_downscale_y_0 << 8) |

			(pre_down->pre_downscale_y_1 << 12);



	SDE_REG_WRITE(&ctx->hw, SSPP_PRE_DOWN_SCALE + idx, val);

}



static u32 _sde_hw_sspp_get_scaler3_ver(struct sde_hw_pipe *ctx)

{

	u32 idx;
@@ -1242,6 +1259,9 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
			c->ops.setup_scaler = reg_dmav1_setup_vig_qseed3;

	}



	if (test_bit(SDE_SSPP_PREDOWNSCALE, &features))

		c->ops.setup_pre_downscale = sde_hw_sspp_setup_pre_downscale;



	if (test_bit(SDE_PERF_SSPP_SYS_CACHE, &perf_features))

		c->ops.setup_sys_cache = sde_hw_sspp_setup_sys_cache;

msm/sde/sde_hw_sspp.h

+8 −0
Original line number Diff line number Diff line
@@ -516,6 +516,14 @@ struct sde_hw_sspp_ops { 
			struct sde_hw_scaler3_cfg *scaler3_cfg,

			u32 offset);



	/**

	 * setup_pre_downscale - setup pre-downscaler for inline rotation

	 * @ctx: Pointer to pipe context

	 * @pre_down: Pointer to pre-downscaler configuration

	 */

	void (*setup_pre_downscale)(struct sde_hw_pipe *ctx,

		struct sde_hw_inline_pre_downscale_cfg *pre_down);



	/**

	 * get_scaler_ver - get scaler h/w version

	 * @ctx: Pointer to pipe context

msm/sde/sde_hw_util.h

+7 −0
Original line number Diff line number Diff line
@@ -160,6 +160,13 @@ struct sde_hw_scaler3_lut_cfg { 
	size_t sep_len;

};



struct sde_hw_inline_pre_downscale_cfg {

	u32 pre_downscale_x_0;

	u32 pre_downscale_x_1;

	u32 pre_downscale_y_0;

	u32 pre_downscale_y_1;

};



u32 *sde_hw_util_get_log_mask_ptr(void);



void sde_reg_write(struct sde_hw_blk_reg_map *c,