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Commit 5ffc3e2d authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "mmc: core: Add at least 3 mclk cycle delay before next command after ACMD41"

parents 7dda60b9 1367cac7

drivers/mmc/core/mmc_ops.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -207,6 +207,18 @@ int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) 
	if (rocr && !mmc_host_is_spi(host))

	if (rocr && !mmc_host_is_spi(host))

		*rocr = cmd.resp[0];

		*rocr = cmd.resp[0];





	/*

	 * As per design, internal CRC error flag will be cleared after 3

	 * MCLK once clear command issued. Since the MCLK will be running

	 * at 400KHz during initialization, design is taking max of 7.5us

	 * to clear the status. So if the CMD_CRC_CHECK_EN bit is enabled

	 * before the source is cleared, CRC INTR bit will be set in the 17th

	 * bit of INTR status register. So it expected to issue the next

	 * command and enable CMD_CRC_CHK_EN after 7.5us (3*MCLK) delay.

	 */

	if (!err)

		udelay(8);



	return err;

	return err;

}

}

drivers/mmc/core/sd_ops.c

+12 −0
Original line number Original line Diff line number Diff line
@@ -155,6 +155,18 @@ int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr) 
	if (rocr && !mmc_host_is_spi(host))

	if (rocr && !mmc_host_is_spi(host))

		*rocr = cmd.resp[0];

		*rocr = cmd.resp[0];





	/*

	 * As per design, internal CRC error flag will be cleared after 3

	 * MCLK once clear command issued. Since the MCLK will be running

	 * at 400KHz during initialization, design is taking max of 7.5us

	 * to clear the status. So if the CMD_CRC_CHECK_EN bit is enabled

	 * before the source is cleared, CRC INTR bit will be set in the 17th

	 * bit of INTR status register. So it expected to issue the next

	 * command and enable CMD_CRC_CHK_EN after 7.5us (3*MCLK) delay.

	 */

	if (!err)

		udelay(8);



	return err;

	return err;

}

}