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Commit 5fb181cb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Thomas Gleixner:
 "Two fixes for perf x86 hardware implementations:

   - Restrict the period on Nehalem machines to prevent perf from
     hogging the CPU

   - Prevent the AMD IBS driver from overwriting the hardwre controlled
     and pre-seeded reserved bits (0-6) in the count register which
     caused a sample bias for dispatched micro-ops"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf/x86/amd/ibs: Fix sample bias for dispatched micro-ops
  perf/x86/intel: Restrict period on Nehalem
parents 5358e6e7 0f4cd769

arch/x86/events/amd/ibs.c

+10 −3
Original line number Diff line number Diff line
@@ -661,10 +661,17 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs) 


	throttle = perf_event_overflow(event, &data, &regs);

out:

	if (throttle)

	if (throttle) {

		perf_ibs_stop(event, 0);

	else

		perf_ibs_enable_event(perf_ibs, hwc, period >> 4);

	} else {

		period >>= 4;



		if ((ibs_caps & IBS_CAPS_RDWROPCNT) &&

		    (*config & IBS_OP_CNT_CTL))

			period |= *config & IBS_OP_CUR_CNT_RAND;



		perf_ibs_enable_event(perf_ibs, hwc, period);

	}



	perf_event_update_userpage(event);

arch/x86/events/intel/core.c

+6 −0
Original line number Diff line number Diff line
@@ -3572,6 +3572,11 @@ static u64 bdw_limit_period(struct perf_event *event, u64 left) 
	return left;

}



static u64 nhm_limit_period(struct perf_event *event, u64 left)

{

	return max(left, 32ULL);

}



PMU_FORMAT_ATTR(event,	"config:0-7"	);

PMU_FORMAT_ATTR(umask,	"config:8-15"	);

PMU_FORMAT_ATTR(edge,	"config:18"	);
@@ -4606,6 +4611,7 @@ __init int intel_pmu_init(void) 
		x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints;

		x86_pmu.enable_all = intel_pmu_nhm_enable_all;

		x86_pmu.extra_regs = intel_nehalem_extra_regs;

		x86_pmu.limit_period = nhm_limit_period;



		mem_attr = nhm_mem_events_attrs;

arch/x86/include/asm/perf_event.h

+8 −4
Original line number Diff line number Diff line
@@ -252,16 +252,20 @@ struct pebs_lbr { 
#define IBSCTL_LVT_OFFSET_VALID		(1ULL<<8)

#define IBSCTL_LVT_OFFSET_MASK		0x0F



/* ibs fetch bits/masks */

/* IBS fetch bits/masks */

#define IBS_FETCH_RAND_EN	(1ULL<<57)

#define IBS_FETCH_VAL		(1ULL<<49)

#define IBS_FETCH_ENABLE	(1ULL<<48)

#define IBS_FETCH_CNT		0xFFFF0000ULL

#define IBS_FETCH_MAX_CNT	0x0000FFFFULL



/* ibs op bits/masks */

/* lower 4 bits of the current count are ignored: */

#define IBS_OP_CUR_CNT		(0xFFFF0ULL<<32)

/*

 * IBS op bits/masks

 * The lower 7 bits of the current count are random bits

 * preloaded by hardware and ignored in software

 */

#define IBS_OP_CUR_CNT		(0xFFF80ULL<<32)

#define IBS_OP_CUR_CNT_RAND	(0x0007FULL<<32)

#define IBS_OP_CNT_CTL		(1ULL<<19)

#define IBS_OP_VAL		(1ULL<<18)

#define IBS_OP_ENABLE		(1ULL<<17)