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Commit 5f926e88 authored by Marc Zyngier's avatar Marc Zyngier Committed by Gregory CLEMENT
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ARM64: dts: marvell: armada-37xx: Enable memory-mapped GIC CPU interface 



The Cortex-A53s that power the Armada-37xx SoCs are equipped with
a GIC CPU interface that gets enabled when coupled with a GICv3
interrupt controller, such as the GIC-500 on the this SoC.

Advertise the MMIO ranges provided by the CPUs, which enables
(among other things) GICv2 guests to run under a hypervisor such
as KVM.

Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
parent 95696d29

arch/arm64/boot/dts/marvell/armada-37xx.dtsi

+4 −1
Original line number Diff line number Diff line
@@ -322,7 +322,10 @@ 
				#interrupt-cells = <3>;

				interrupt-controller;

				reg = <0x1d00000 0x10000>, /* GICD */

				      <0x1d40000 0x40000>; /* GICR */

				      <0x1d40000 0x40000>, /* GICR */

				      <0x1d80000 0x2000>,  /* GICC */

				      <0x1d90000 0x2000>,  /* GICH */

				      <0x1da0000 0x20000>; /* GICV */

				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

			};

		};