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Commit 5ebc4f0d authored by Sarthak Garg's avatar Sarthak Garg
Browse files

mmc: sdhci-msm: Calculate timeout value based on the base clock 



Qcom SDHC uses base clock in calculating the data-timeout
value. So set SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK quirk.

The controller internally multiplies the timeout control register
value by 4 while calculating the data timeout, so set timeout_clk_div
as 4 to get the correct data-timeout counter value correctly.

Change-Id: I73feb37f92b4a7a0d740a262a4c68ec458e6d154
Suggested-by: default avatarVeerabhadrarao Badiganti <vbadigan@codeaurora.org>
Signed-off-by: default avatarSarthak Garg <sartgarg@codeaurora.org>
parent 6ab3e82f

drivers/mmc/host/sdhci-msm.c

+3 −1
Original line number Diff line number Diff line
@@ -3012,7 +3012,8 @@ static const struct sdhci_pltfm_data sdhci_msm_pdata = { 
		  SDHCI_QUIRK_SINGLE_POWER_WRITE |

		  SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |

		  SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |

		  SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,

		  SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12 |

		  SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,



	.quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,

	.ops = &sdhci_msm_ops,
@@ -3302,6 +3303,7 @@ static int sdhci_msm_probe(struct platform_device *pdev) 
	msm_host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_NEED_RSP_BUSY;



#if defined(CONFIG_SDC_QTI)

	host->timeout_clk_div = 4;

	msm_host->mmc->caps2 |= MMC_CAP2_CLK_SCALE;

#endif

	pm_runtime_get_noresume(&pdev->dev);