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Commit 5e5b9f62 authored by Tariq Toukan's avatar Tariq Toukan Committed by David S. Miller
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net/mlx4_core: A write memory barrier is sufficient in EQ ci update 



Soften the memory barrier call of mb() by a sufficient wmb() in the
consumer index update of the event queues.

Suggested-by: default avatarEric Dumazet <edumazet@google.com>
Signed-off-by: default avatarTariq Toukan <tariqt@mellanox.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 254764e5

drivers/net/ethernet/mellanox/mlx4/eq.c

+1 −1
Original line number Diff line number Diff line
@@ -100,7 +100,7 @@ static void eq_set_ci(struct mlx4_eq *eq, int req_not) 
					       req_not << 31),

		     eq->doorbell);

	/* We still want ordering, just not swabbing, so add a barrier */

	mb();

	wmb();

}



static struct mlx4_eqe *get_eqe(struct mlx4_eq *eq, u32 entry, u8 eqe_factor,