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Commit 5de46e81 authored by Yuanfang Zhang's avatar Yuanfang Zhang
Browse files

coresight: fix etr pice mode issue 



Only start the sw mode when pcie_path is configured as sw.

Change-Id: I3b9fb890008760b0a25827bb039cd378512f4efe
Signed-off-by: default avatarYuanfang Zhang <zhangyuanfang@codeaurora.org>
parent f6eb6018

drivers/hwtracing/coresight/coresight-byte-cntr.c

+2 −1
Original line number Diff line number Diff line
@@ -674,7 +674,8 @@ static void etr_pcie_client_cb(struct mhi_dev_client_cb_data *cb_data) 
	byte_cntr_data = cb_data->user_data;

	if (!byte_cntr_data)

		return;



	if (tmcdrvdata->pcie_path != TMC_ETR_PCIE_SW_PATH)

		return;

	switch (cb_data->ctrl_info) {

	case  MHI_STATE_CONNECTED:

		if (cb_data->channel == byte_cntr_data->pcie_out_chan) {

drivers/hwtracing/coresight/coresight-tmc-etr.c

+0 −2
Original line number Diff line number Diff line
@@ -1706,8 +1706,6 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev) 


	if (drvdata->out_mode == TMC_ETR_OUT_MODE_MEM)

		tmc_etr_byte_cntr_start(drvdata->byte_cntr);

	if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE)

		etr_pcie_start(drvdata->byte_cntr);



	if (drvdata->out_mode == TMC_ETR_OUT_MODE_PCIE

			&& drvdata->pcie_path == TMC_ETR_PCIE_SW_PATH)