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Commit 5d97af31 authored by David Dai's avatar David Dai
Browse files

ARM: dts: msm: Add interconnect l3 epss devices for Lahaina 

Add a device that allows for individual CPU votes and
a shared device used for aggregate voting.

Change-Id: Ib4eea75719c4f27f919732d20cb3bb130635acda
parent 0b987936

qcom/lahaina.dtsi

+19 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,videocc-lahaina.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interconnect/qcom,epss-l3.h>

#include <dt-bindings/interconnect/qcom,lahaina.h>

#include <dt-bindings/soc/qcom,ipcc.h>

#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -949,6 +950,24 @@ 
		qcom,bcm-voters = <&apps_bcm_voter>;

	};



	epss_l3_shared: l3_shared@18590000 {

		reg = <0x18590000 0x1000>;

		compatible = "qcom,lahaina-epss-l3-shared";

		#interconnect-cells = <1>;

		clock-names = "xo", "alternate";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_GPLL0>;

	};



	epss_l3_cpu: l3_cpu@18590000 {

		reg = <0x18590000 0x4000>;

		compatible = "qcom,lahaina-epss-l3-cpu";

		#interconnect-cells = <1>;

		clock-names = "xo", "alternate";

		clocks = <&clock_rpmh RPMH_CXO_CLK>,

			<&clock_gcc GCC_GPLL0>;

	};



	pil_scm_pas {

		compatible = "qcom,pil-tz-scm-pas";

		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;