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Commit 5d87a3fd authored by SivapiriyanKumarasamy's avatar SivapiriyanKumarasamy Committed by Alex Deucher
Browse files

drm/amd/display: Add PSR SMU Interrupt support 



[WHY]
We have new bios capabilities enabling s0i2 entry on SMU interrupt. We want
this interrupt to be fired on PSR transitions such that we enter s0i2
when entering PSR active.

[HOW]
Add code to send the SMU interrupt with the appropriate
staticscreen flag when entering and exting PSR. Protect this
code with a config flag since it currently impacts BL PWM.

Signed-off-by: default avatarSivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com>
Reviewed-by: default avatarAnthony Koo <Anthony.Koo@amd.com>
Acked-by: default avatarLeo Li <sunpeng.li@amd.com>
Acked-by: default avatarTony Cheng <Tony.Cheng@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 148cccf2

drivers/gpu/drm/amd/display/dc/dc_types.h

+2 −1
Original line number Diff line number Diff line
@@ -550,9 +550,9 @@ struct psr_config { 
	unsigned char psr_version;

	unsigned int psr_rfb_setup_time;

	bool psr_exit_link_training_required;



	bool psr_frame_capture_indication_req;

	unsigned int psr_sdp_transmit_line_num_deadline;

	bool allow_smu_optimizations;

};



union dmcu_psr_level {
@@ -654,6 +654,7 @@ struct psr_context { 
	 * continuing powerd own

	 */

	unsigned int frame_delay;

	bool allow_smu_optimizations;

};



struct colorspace_transform {

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c

+3 −4
Original line number Diff line number Diff line
@@ -213,9 +213,6 @@ static bool dce_dmcu_setup_psr(struct dmcu *dmcu, 
	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,

			psr_context->sdpTransmitLineNumDeadline);



	if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)

		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);



	/* waitDMCUReadyForCmd */

	REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,

					dmcu_wait_reg_ready_interval,
@@ -594,7 +591,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 
	link->link_enc->funcs->psr_program_secondary_packet(link->link_enc,

			psr_context->sdpTransmitLineNumDeadline);



	if (psr_context->psr_level.bits.SKIP_SMU_NOTIFICATION)

	if (psr_context->allow_smu_optimizations)

		REG_UPDATE(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, 1);



	/* waitDMCUReadyForCmd */
@@ -615,6 +612,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 
			psr_context->psrFrameCaptureIndicationReq;

	masterCmdData1.bits.aux_chan = psr_context->channel;

	masterCmdData1.bits.aux_repeat = psr_context->aux_repeats;

	masterCmdData1.bits.allow_smu_optimizations = psr_context->allow_smu_optimizations;

	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1),

					masterCmdData1.u32All);
@@ -635,6 +633,7 @@ static bool dcn10_dmcu_setup_psr(struct dmcu *dmcu, 
	dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3),

			masterCmdData3.u32All);





	/* setDMCUParam_Cmd */

	REG_UPDATE(MASTER_COMM_CMD_REG,

			MASTER_COMM_CMD_REG_BYTE0, PSR_SET);

drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.h

+11 −11
Original line number Diff line number Diff line
@@ -208,7 +208,7 @@ union dce_dmcu_psr_config_data_reg1 { 
		unsigned int frame_cap_ind:1;                    /*[23:23]*/

		unsigned int aux_chan:3;                         /*[26:24]*/

		unsigned int aux_repeat:4;                       /*[30:27]*/

		unsigned int reserved:1;           /*[31:31]*/

		unsigned int allow_smu_optimizations:1;         /*[31:31]*/

	} bits;

	unsigned int u32All;

};