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Commit 5d5c303e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'mips_fixes_5.0_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux 

Pull MIPS fixes from Paul Burton:

 - Fix IPI handling for Lantiq SoCs, which was broken by changes made
   back in v4.12.

 - Enable OF/DT serial support in ath79_defconfig to give us working
   serial by default.

 - Fix 64b builds for the Jazz platform.

 - Set up a struct device for the BCM47xx SoC to allow BCM47xx drivers
   to perform DMA again following the major DMA mapping changes made in
   v4.19.

 - Disable MSI on Cavium Octeon systems when the pcie_disable command
   line parameter introduced in v3.3 is used, in order to avoid
   inadvetently accessing PCIe controller registers despite the command
   line.

 - Fix a build failure for Cavium Octeon kernels with kexec enabled,
   introduced in v4.20.

 - Fix a regression in the behaviour of semctl/shmctl/msgctl IPC
   syscalls for kernels including n32 support but not o32 support caused
   by some cleanup in v3.19.

* tag 'mips_fixes_5.0_2' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux:
  MIPS: OCTEON: fix kexec support
  mips: fix n32 compat_ipc_parse_version
  Disable MSI also when pcie-octeon.pcie_disable on
  MIPS: BCM47XX: Setup struct device for the SoC
  MIPS: jazz: fix 64bit build
  MIPS: ath79: Enable OF serial ports in the default config
  MIPS: lantiq: Use CP0_LEGACY_COMPARE_IRQ
  MIPS: lantiq: Fix IPI interrupt handling
parents 6a0141a0 8a644c64

arch/mips/Kconfig

+1 −0
Original line number Diff line number Diff line
@@ -3155,6 +3155,7 @@ config MIPS32_O32 
config MIPS32_N32

	bool "Kernel support for n32 binaries"

	depends on 64BIT

	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION

	select COMPAT

	select MIPS32_COMPAT

	select SYSVIPC_COMPAT if SYSVIPC

arch/mips/bcm47xx/setup.c

+31 −0
Original line number Diff line number Diff line
@@ -173,6 +173,31 @@ void __init plat_mem_setup(void) 
	pm_power_off = bcm47xx_machine_halt;

}



#ifdef CONFIG_BCM47XX_BCMA

static struct device * __init bcm47xx_setup_device(void)

{

	struct device *dev;

	int err;



	dev = kzalloc(sizeof(*dev), GFP_KERNEL);

	if (!dev)

		return NULL;



	err = dev_set_name(dev, "bcm47xx_soc");

	if (err) {

		pr_err("Failed to set SoC device name: %d\n", err);

		kfree(dev);

		return NULL;

	}



	err = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));

	if (err)

		pr_err("Failed to set SoC DMA mask: %d\n", err);



	return dev;

}

#endif



/*

 * This finishes bus initialization doing things that were not possible without

 * kmalloc. Make sure to call it late enough (after mm_init).
@@ -183,6 +208,10 @@ void __init bcm47xx_bus_setup(void) 
	if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {

		int err;



		bcm47xx_bus.bcma.dev = bcm47xx_setup_device();

		if (!bcm47xx_bus.bcma.dev)

			panic("Failed to setup SoC device\n");



		err = bcma_host_soc_init(&bcm47xx_bus.bcma);

		if (err)

			panic("Failed to initialize BCMA bus (err %d)", err);
@@ -235,6 +264,8 @@ static int __init bcm47xx_register_bus_complete(void) 
#endif

#ifdef CONFIG_BCM47XX_BCMA

	case BCM47XX_BUS_TYPE_BCMA:

		if (device_register(bcm47xx_bus.bcma.dev))

			pr_err("Failed to register SoC device\n");

		bcma_bus_register(&bcm47xx_bus.bcma.bus);

		break;

#endif

arch/mips/cavium-octeon/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ static void octeon_kexec_smp_down(void *ignored) 
	"	sync						\n"

	"	synci	($0)					\n");



	relocated_kexec_smp_wait(NULL);

	kexec_reboot();

}

#endif

arch/mips/configs/ath79_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -66,6 +66,7 @@ CONFIG_SERIAL_8250_CONSOLE=y 
# CONFIG_SERIAL_8250_PCI is not set

CONFIG_SERIAL_8250_NR_UARTS=1

CONFIG_SERIAL_8250_RUNTIME_UARTS=1

CONFIG_SERIAL_OF_PLATFORM=y

CONFIG_SERIAL_AR933X=y

CONFIG_SERIAL_AR933X_CONSOLE=y

# CONFIG_HW_RANDOM is not set

arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h

+0 −2
Original line number Diff line number Diff line
@@ -18,8 +18,6 @@ 
#define INT_NUM_EXTRA_START		(INT_NUM_IM4_IRL0 + 32)

#define INT_NUM_IM_OFFSET		(INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0)



#define MIPS_CPU_TIMER_IRQ			7



#define MAX_IM			5



#endif /* _FALCON_IRQ__ */