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Commit 5d4545ae authored by Ben Widawsky's avatar Ben Widawsky Committed by Daniel Vetter
Browse files

drm/i915: Create a gtt structure 



The purpose of the gtt structure is to help isolate our gtt specific
properties from the rest of the code (in doing so it help us finish the
isolation from the AGP connection).

The following members are pulled out (and renamed):
gtt_start
gtt_total
gtt_mappable_end
gtt_mappable
gtt_base_addr
gsm

The gtt structure will serve as a nice place to put gen specific gtt
routines in upcoming patches. As far as what else I feel belongs in this
structure: it is meant to encapsulate the GTT's physical properties.
This is why I've not added fields which track various drm_mm properties,
or things like gtt_mtrr (which is itself a pretty transient field).

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@gmail.com>
[Ben modified commit messages]
Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 00fc2c3c

drivers/gpu/drm/i915/i915_debugfs.c

+2 −2
Original line number Diff line number Diff line
@@ -259,8 +259,8 @@ static int i915_gem_object_info(struct seq_file *m, void* data) 
		   count, size);



	seq_printf(m, "%zu [%zu] gtt total\n",

		   dev_priv->mm.gtt_total,

		   dev_priv->mm.gtt_mappable_end - dev_priv->mm.gtt_start);

		   dev_priv->gtt.total,

		   dev_priv->gtt.mappable_end - dev_priv->gtt.start);



	mutex_unlock(&dev->struct_mutex);

drivers/gpu/drm/i915/i915_dma.c

+10 −10
Original line number Diff line number Diff line
@@ -1076,7 +1076,7 @@ static int i915_set_status_page(struct drm_device *dev, void *data, 
	ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);



	dev_priv->dri1.gfx_hws_cpu_addr =

		ioremap_wc(dev_priv->mm.gtt_base_addr + hws->addr, 4096);

		ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);

	if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {

		i915_dma_cleanup(dev);

		ring->status_page.gfx_addr = 0;
@@ -1543,17 +1543,17 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
	}



	aperture_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;

	dev_priv->mm.gtt_base_addr = dev_priv->mm.gtt->gma_bus_addr;

	dev_priv->gtt.mappable_base = dev_priv->mm.gtt->gma_bus_addr;



	dev_priv->mm.gtt_mapping =

		io_mapping_create_wc(dev_priv->mm.gtt_base_addr,

	dev_priv->gtt.mappable =

		io_mapping_create_wc(dev_priv->gtt.mappable_base,

				     aperture_size);

	if (dev_priv->mm.gtt_mapping == NULL) {

	if (dev_priv->gtt.mappable == NULL) {

		ret = -EIO;

		goto out_rmmap;

	}



	i915_mtrr_setup(dev_priv, dev_priv->mm.gtt_base_addr,

	i915_mtrr_setup(dev_priv, dev_priv->gtt.mappable_base,

			aperture_size);



	/* The i915 workqueue is primarily used for batched retirement of
@@ -1658,11 +1658,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) 
out_mtrrfree:

	if (dev_priv->mm.gtt_mtrr >= 0) {

		mtrr_del(dev_priv->mm.gtt_mtrr,

			 dev_priv->mm.gtt_base_addr,

			 dev_priv->gtt.mappable_base,

			 aperture_size);

		dev_priv->mm.gtt_mtrr = -1;

	}

	io_mapping_free(dev_priv->mm.gtt_mapping);

	io_mapping_free(dev_priv->gtt.mappable);

out_rmmap:

	pci_iounmap(dev->pdev, dev_priv->regs);

put_gmch:
@@ -1696,10 +1696,10 @@ int i915_driver_unload(struct drm_device *dev) 
	/* Cancel the retire work handler, which should be idle now. */

	cancel_delayed_work_sync(&dev_priv->mm.retire_work);



	io_mapping_free(dev_priv->mm.gtt_mapping);

	io_mapping_free(dev_priv->gtt.mappable);

	if (dev_priv->mm.gtt_mtrr >= 0) {

		mtrr_del(dev_priv->mm.gtt_mtrr,

			 dev_priv->mm.gtt_base_addr,

			 dev_priv->gtt.mappable_base,

			 dev_priv->mm.gtt->gtt_mappable_entries * PAGE_SIZE);

		dev_priv->mm.gtt_mtrr = -1;

	}

drivers/gpu/drm/i915/i915_drv.h

+21 −8
Original line number Diff line number Diff line
@@ -364,6 +364,25 @@ struct intel_device_info { 
	u8 has_llc:1;

};



/* The Graphics Translation Table is the way in which GEN hardware translates a

 * Graphics Virtual Address into a Physical Address. In addition to the normal

 * collateral associated with any va->pa translations GEN hardware also has a

 * portion of the GTT which can be mapped by the CPU and remain both coherent

 * and correct (in cases like swizzling). That region is referred to as GMADR in

 * the spec.

 */

struct i915_gtt {

	unsigned long start;		/* Start offset of used GTT */

	size_t total;			/* Total size GTT can map */



	unsigned long mappable_end;	/* End offset that we can CPU map */

	struct io_mapping *mappable;	/* Mapping to our CPU mappable region */

	phys_addr_t mappable_base;	/* PA of our GMADR */



	/** "Graphics Stolen Memory" holds the global PTEs */

	void __iomem *gsm;

};



#define I915_PPGTT_PD_ENTRIES 512

#define I915_PPGTT_PT_ENTRIES 1024

struct i915_hw_ppgtt {
@@ -781,6 +800,8 @@ typedef struct drm_i915_private { 
	/* Register state */

	bool modeset_on_lid;



	struct i915_gtt gtt;



	struct {

		/** Bridge to intel-gtt-ko */

		struct intel_gtt *gtt;
@@ -799,15 +820,8 @@ typedef struct drm_i915_private { 
		struct list_head unbound_list;



		/** Usable portion of the GTT for GEM */

		unsigned long gtt_start;

		unsigned long gtt_mappable_end;

		unsigned long stolen_base; /* limited to low memory (32-bit) */



		/** "Graphics Stolen Memory" holds the global PTEs */

		void __iomem *gsm;



		struct io_mapping *gtt_mapping;

		phys_addr_t gtt_base_addr;

		int gtt_mtrr;



		/** PPGTT used for aliasing the PPGTT with the GTT */
@@ -885,7 +899,6 @@ typedef struct drm_i915_private { 
		struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];



		/* accounting, useful for userland debugging */

		size_t gtt_total;

		size_t object_memory;

		u32 object_count;

	} mm;

drivers/gpu/drm/i915/i915_gem.c

+7 −7
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, 
			pinned += obj->gtt_space->size;

	mutex_unlock(&dev->struct_mutex);



	args->aper_size = dev_priv->mm.gtt_total;

	args->aper_size = dev_priv->gtt.total;

	args->aper_available_size = args->aper_size - pinned;



	return 0;
@@ -637,7 +637,7 @@ i915_gem_gtt_pwrite_fast(struct drm_device *dev, 
		 * source page isn't available.  Return the error and we'll

		 * retry in the slow path.

		 */

		if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,

		if (fast_user_write(dev_priv->gtt.mappable, page_base,

				    page_offset, user_data, page_length)) {

			ret = -EFAULT;

			goto out_unpin;
@@ -1362,7 +1362,7 @@ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) 


	obj->fault_mappable = true;



	pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) +

	pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) +

		page_offset;



	/* Finally, remap it using the new GTT offset */
@@ -1544,7 +1544,7 @@ i915_gem_mmap_gtt(struct drm_file *file, 
		goto unlock;

	}



	if (obj->base.size > dev_priv->mm.gtt_mappable_end) {

	if (obj->base.size > dev_priv->gtt.mappable_end) {

		ret = -E2BIG;

		goto out;

	}
@@ -2910,7 +2910,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, 
	 * before evicting everything in a vain attempt to find space.

	 */

	if (obj->base.size >

	    (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {

	    (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) {

		DRM_ERROR("Attempting to bind an object larger than the aperture\n");

		return -E2BIG;

	}
@@ -2931,7 +2931,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, 
	if (map_and_fenceable)

		ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node,

							  size, alignment, obj->cache_level,

							  0, dev_priv->mm.gtt_mappable_end);

							  0, dev_priv->gtt.mappable_end);

	else

		ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node,

						 size, alignment, obj->cache_level);
@@ -2971,7 +2971,7 @@ i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, 
		(node->start & (fence_alignment - 1)) == 0;



	mappable =

		obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;

		obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end;



	obj->map_and_fenceable = mappable && fenceable;

drivers/gpu/drm/i915/i915_gem_evict.c

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ i915_gem_evict_something(struct drm_device *dev, int min_size, 
	if (mappable)

		drm_mm_init_scan_with_range(&dev_priv->mm.gtt_space,

					    min_size, alignment, cache_level,

					    0, dev_priv->mm.gtt_mappable_end);

					    0, dev_priv->gtt.mappable_end);

	else

		drm_mm_init_scan(&dev_priv->mm.gtt_space,

				 min_size, alignment, cache_level);