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Commit 5cd861d4 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add ION support for Direwolf"

parents e3a906a9 f3b6f39e

bindings/arm/msm/qcom,llcc.txt

+1 −0
Original line number Diff line number Diff line
@@ -15,6 +15,7 @@ Properties: 
	            or "qcom,shima-llcc" or "qcom,sdxlemur-llcc"

	            or "qcom,yupik-llcc" or "qcom,sm8150-llcc"

		    or "qcom,sdmshrike-llcc" or "qcom,sm6150-llcc"

		    or "qcom,direwolf-llcc"

		    "qcom,llcc-v2" must be appended for V2 hardware.



- reg:

qcom/direwolf-ion.dtsi

0 → 100644
+14 −0
Original line number Diff line number Diff line 
#include <dt-bindings/arm/msm/msm_ion_ids.h>



&soc {

	msm_ion: qcom,ion {

		compatible = "qcom,msm-ion";

		#address-cells = <1>;

		#size-cells = <0>;



		system_heap: qcom,ion-heap@25 {

			reg = <ION_SYSTEM_HEAP_ID>;

			qcom,ion-heap-type = "MSM_SYSTEM";

		};

	};

};

qcom/direwolf.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -1082,6 +1082,16 @@ 
		#mbox-cells = <1>;

	};



	cache-controller@9200000 {

		compatible = "qcom,direwolf-llcc", "qcom,llcc-v2";

		reg = <0x9200000 0x1d0000> , <0x9600000 0x50000>;

		reg-names = "llcc_base", "llcc_broadcast_base";

		cap-based-alloc-and-pwr-collapse;

		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&aopcc QDSS_CLK>;

		clock-names = "qdss_clk";

	};



	llcc_pmu: llcc-pmu@9095000 {

		compatible = "qcom,llcc-pmu-ver2";

		reg = <0x09095000 0x300>;
@@ -1482,6 +1492,7 @@ 
#include "direwolf-regulators.dtsi"

#include "direwolf-pm.dtsi"

#include "direwolf-gdsc.dtsi"

#include "direwolf-ion.dtsi"



&gcc_emac0_gdsc {

	status = "ok";