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Commit 5ccd3bd9 authored by Russell King's avatar Russell King
Browse files

Merge branches 'fixes' and 'misc' 



Fix up the conflict between "VDSO: Drop implicit common-page-size
linker flag" and "vdso: pass --be8 to linker if necessary"

Signed-off-by: default avatarRussell King <rmk+kernel@armlinux.org.uk>
parents c5d0e49e f785b42f

arch/arm/Kconfig

+30 −0
Original line number Diff line number Diff line
@@ -1175,6 +1175,14 @@ config ARM_ERRATA_825619 
	  DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable

	  and Device/Strongly-Ordered loads and stores might cause deadlock



config ARM_ERRATA_857271

	bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"

	depends on CPU_V7

	help

	  This option enables the workaround for the 857271 Cortex-A12

	  (all revs) erratum. Under very rare timing conditions, the CPU might

	  hang. The workaround is expected to have a < 1% performance impact.



config ARM_ERRATA_852421

	bool "ARM errata: A17: DMB ST might fail to create order between stores"

	depends on CPU_V7
@@ -1196,6 +1204,16 @@ config ARM_ERRATA_852423 
	  config option from the A12 erratum due to the way errata are checked

	  for and handled.



config ARM_ERRATA_857272

	bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"

	depends on CPU_V7

	help

	  This option enables the workaround for the 857272 Cortex-A17 erratum.

	  This erratum is not known to be fixed in any A17 revision.

	  This is identical to Cortex-A12 erratum 857271.  It is a separate

	  config option from the A12 erratum due to the way errata are checked

	  for and handled.



endmenu



source "arch/arm/common/Kconfig"
@@ -1232,6 +1250,18 @@ config PCI_HOST_ITE8152 
	default y

	select DMABOUNCE



config ARM_ERRATA_814220

	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"

	depends on CPU_V7

	help

	  The v7 ARM states that all cache and branch predictor maintenance

	  operations that do not specify an address execute, relative to

	  each other, in program order.

	  However, because of this erratum, an L2 set/way cache maintenance

	  operation can overtake an L1 set/way cache maintenance operation.

	  This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,

	  r0p4, r0p5.



endmenu



menu "Kernel Features"

arch/arm/configs/exynos_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -9,6 +9,7 @@ CONFIG_MODULE_UNLOAD=y 
CONFIG_PARTITION_ADVANCED=y

CONFIG_ARCH_EXYNOS=y

CONFIG_ARCH_EXYNOS3=y

CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND=y

CONFIG_SMP=y

CONFIG_BIG_LITTLE=y

CONFIG_NR_CPUS=8

arch/arm/include/asm/bug.h

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ void hook_ifault_code(int nr, int (*fn)(unsigned long, unsigned int, 
extern asmlinkage void c_backtrace(unsigned long fp, int pmode);



struct mm_struct;

extern void show_pte(struct mm_struct *mm, unsigned long addr);

void show_pte(const char *lvl, struct mm_struct *mm, unsigned long addr);

extern void __show_regs(struct pt_regs *);



#endif

arch/arm/include/asm/cacheflush.h

+7 −0
Original line number Diff line number Diff line
@@ -479,4 +479,11 @@ static inline void __sync_cache_range_r(volatile void *p, size_t size) 
void flush_uprobe_xol_access(struct page *page, unsigned long uaddr,

			     void *kaddr, unsigned long len);





#ifdef CONFIG_CPU_ICACHE_MISMATCH_WORKAROUND

void check_cpu_icache_size(int cpuid);

#else

static inline void check_cpu_icache_size(int cpuid) { }

#endif



#endif

arch/arm/kernel/smp.c

+1 −0
Original line number Diff line number Diff line
@@ -375,6 +375,7 @@ static void smp_store_cpu_info(unsigned int cpuid) 
	cpu_info->cpuid = read_cpuid_id();



	store_cpu_topology(cpuid);

	check_cpu_icache_size(cpuid);

}



/*