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Commit 5c6e116d authored by Seiya Wang's avatar Seiya Wang Committed by Matthias Brugger
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arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72 



The cpu type of cpu2 and cpu3 should be cortex-a72, not cortex-a57.

Signed-off-by: default avatarSeiya Wang <seiya.wang@mediatek.com>
Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 69697063

arch/arm64/boot/dts/mediatek/mt8173.dtsi

+4 −4
Original line number Diff line number Diff line
@@ -178,12 +178,12 @@ 


		cpu2: cpu@100 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			compatible = "arm,cortex-a72";

			reg = <0x100>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			#cooling-cells = <2>;

			clocks = <&infracfg CLK_INFRA_CA57SEL>,

			clocks = <&infracfg CLK_INFRA_CA72SEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";

			operating-points-v2 = <&cluster1_opp>;
@@ -191,12 +191,12 @@ 


		cpu3: cpu@101 {

			device_type = "cpu";

			compatible = "arm,cortex-a57";

			compatible = "arm,cortex-a72";

			reg = <0x101>;

			enable-method = "psci";

			cpu-idle-states = <&CPU_SLEEP_0>;

			#cooling-cells = <2>;

			clocks = <&infracfg CLK_INFRA_CA57SEL>,

			clocks = <&infracfg CLK_INFRA_CA72SEL>,

				 <&apmixedsys CLK_APMIXED_MAINPLL>;

			clock-names = "cpu", "intermediate";

			operating-points-v2 = <&cluster1_opp>;