Loading bindings/mdss-pll.txtdeleted 100644 → 0 +0 −108 Original line number Diff line number Diff line Qualcomm Technologies, Inc. MDSS pll for DSI/EDP/HDMI mdss-pll is a pll controller device which supports pll devices that are compatible with MIPI display serial interface specification, HDMI and edp. Required properties: - compatible: Compatible name used in the driver. Should be one of: "qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939", "qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909", "qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994", "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992", "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996", "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", "qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8", "qcom,mdss_dsi_pll_10nm", "qcom,mdss_dp_pll_8998", "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm", "qcom,mdss_dsi_pll_7nm", "qcom,mdss_dp_pll_7nm", "qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm", "qcom,mdss_dp_pll_14nm", "qcom,mdss_dsi_pll_7nm_v2", "qcom,mdss_hdmi_pll_28lpm","qcom,mdss_dsi_pll_7nm_v4_1", "qcom,mdss_dp_pll_7nm_v2" - cell-index: Specifies the controller used - reg: offset and length of the register set for the device. - reg-names : names to refer to register sets related to this device - gdsc-supply: Phandle for gdsc regulator device node. - vddio-supply: Phandle for vddio regulator device node. - clocks: List of Phandles for clock device nodes needed by the device. - clock-names: List of clock names needed by the device. - clock-rate: List of clock rates in Hz. Optional properties: - label: A string used to describe the driver used. - vcca-supply: Phandle for vcca regulator device node. - qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. - qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" or "center-spread". Default is "down-spread" if it is not specified. - qcom,ssc-frequency-hz: Integer property to specify the spread frequency to be programmed for the SSC. - qcom,ssc-ppm: Integer property to specify the Parts per Million value of SSC. - qcom,platform-supply-entries: A node that lists the elements of the supply. There can be more than one instance of this binding, in which case the entry would be appended with the supply entry index. e.g. qcom,platform-supply-entry@0 - reg: offset and length of the register set for the device. -- qcom,supply-name: name of the supply (vdd/vdda/vddio) -- qcom,supply-min-voltage: minimum voltage level (uV) -- qcom,supply-max-voltage: maximum voltage level (uV) -- qcom,supply-enable-load: load drawn (uA) from enabled supply -- qcom,supply-disable-load: load drawn (uA) from disabled supply -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off Example: mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 { compatible = "qcom,mdss_dsi_pll_8974"; label = "MDSS DSI 0 PLL"; cell-index = <0>; reg = <0xfd922A00 0xD4>, <0xfd922900 0x64>, <0xfd8c2300 0x8>; reg-names = "pll_base", "dynamic_pll_base", "gdsc_base"; gdsc-supply = <&gdsc_mdss>; vddio-supply = <&pm8941_l12>; vcca-supply = <&pm8941_l28>; clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>; clock-names = "mdp_core_clk", "iface_clk", "bus_clk"; clock-rate = <0>, <0>, <0>; qcom,dsi-pll-slave; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; qcom,ssc-frequency-hz = <30000>; qcom,ssc-ppm = <5000>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <100000>; qcom,supply-disable-load = <100>; qcom,supply-pre-on-sleep = <0>; qcom,supply-post-on-sleep = <20>; qcom,supply-pre-off-sleep = <0>; qcom,supply-post-off-sleep = <0>; }; }; }; bindings/sde-dsi.txt +13 −3 Original line number Diff line number Diff line Loading @@ -3,17 +3,18 @@ Qualcomm Technologies, Inc. mdss-dsi is the master DSI device which supports multiple DSI host controllers that are compatible with MIPI display serial interface specification. DSI Controller: DSI Controller and PHY: Required properties: - compatible: Should be "qcom,dsi-ctrl-hw-v<version>". Supported versions include 1.4, 2.0 and 2.2. eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0, qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, qcom,dsi-ctrl-hw-v2.4 qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5 And for dsi phy driver: qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm, qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1 qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2 - reg: Base address and length of DSI controller's memory mapped regions. - reg-names: A list of strings that name the list of regs. Loading @@ -32,6 +33,8 @@ Required properties: "core_clk" "byte_clk_rcg" "pixel_clk_rcg" - pll-label Supported versions of DSI PLL: dsi_pll_5nm - gdsc-supply: phandle to gdsc regulator node. - vdda-supply: phandle to vdda regulator node. - vcca-supply: phandle to vcca regulator node. Loading Loading @@ -116,3 +119,10 @@ Optional properties: specified in Documentation/devicetree/bindings/graph.txt. Video port 0 reg 0 is for the bridge output. The remote endpoint phandle should be mipi_dsi_device device node. - qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. - qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" or "center-spread". Default is "down-spread" if it is not specified. - qcom,ssc-frequency-hz: Integer property to specify the spread frequency to be programmed for the SSC. - qcom,ssc-ppm: Integer property to specify the Parts per Million value of SSC. Loading
bindings/mdss-pll.txtdeleted 100644 → 0 +0 −108 Original line number Diff line number Diff line Qualcomm Technologies, Inc. MDSS pll for DSI/EDP/HDMI mdss-pll is a pll controller device which supports pll devices that are compatible with MIPI display serial interface specification, HDMI and edp. Required properties: - compatible: Compatible name used in the driver. Should be one of: "qcom,mdss_dsi_pll_8916", "qcom,mdss_dsi_pll_8939", "qcom,mdss_dsi_pll_8974", "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8994", "qcom,mdss_dsi_pll_8909", "qcom,mdss_hdmi_pll", "qcom,mdss_hdmi_pll_8994", "qcom,mdss_dsi_pll_8992", "qcom,mdss_hdmi_pll_8992", "qcom,mdss_dsi_pll_8996", "qcom,mdss_hdmi_pll_8996", "qcom,mdss_hdmi_pll_8996_v2", "qcom,mdss_dsi_pll_8996_v2", "qcom,mdss_hdmi_pll_8996_v3", "qcom,mdss_hdmi_pll_8996_v3_1p8", "qcom,mdss_edp_pll_8996_v3", "qcom,mdss_edp_pll_8996_v3_1p8", "qcom,mdss_dsi_pll_10nm", "qcom,mdss_dp_pll_8998", "qcom,mdss_hdmi_pll_8998", "qcom,mdss_dp_pll_10nm", "qcom,mdss_dsi_pll_7nm", "qcom,mdss_dp_pll_7nm", "qcom,mdss_dsi_pll_28lpm", "qcom,mdss_dsi_pll_14nm", "qcom,mdss_dp_pll_14nm", "qcom,mdss_dsi_pll_7nm_v2", "qcom,mdss_hdmi_pll_28lpm","qcom,mdss_dsi_pll_7nm_v4_1", "qcom,mdss_dp_pll_7nm_v2" - cell-index: Specifies the controller used - reg: offset and length of the register set for the device. - reg-names : names to refer to register sets related to this device - gdsc-supply: Phandle for gdsc regulator device node. - vddio-supply: Phandle for vddio regulator device node. - clocks: List of Phandles for clock device nodes needed by the device. - clock-names: List of clock names needed by the device. - clock-rate: List of clock rates in Hz. Optional properties: - label: A string used to describe the driver used. - vcca-supply: Phandle for vcca regulator device node. - qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. - qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" or "center-spread". Default is "down-spread" if it is not specified. - qcom,ssc-frequency-hz: Integer property to specify the spread frequency to be programmed for the SSC. - qcom,ssc-ppm: Integer property to specify the Parts per Million value of SSC. - qcom,platform-supply-entries: A node that lists the elements of the supply. There can be more than one instance of this binding, in which case the entry would be appended with the supply entry index. e.g. qcom,platform-supply-entry@0 - reg: offset and length of the register set for the device. -- qcom,supply-name: name of the supply (vdd/vdda/vddio) -- qcom,supply-min-voltage: minimum voltage level (uV) -- qcom,supply-max-voltage: maximum voltage level (uV) -- qcom,supply-enable-load: load drawn (uA) from enabled supply -- qcom,supply-disable-load: load drawn (uA) from disabled supply -- qcom,supply-pre-on-sleep: time to sleep (ms) before turning on -- qcom,supply-post-on-sleep: time to sleep (ms) after turning on -- qcom,supply-pre-off-sleep: time to sleep (ms) before turning off -- qcom,supply-post-off-sleep: time to sleep (ms) after turning off Example: mdss_dsi0_pll: qcom,mdss_dsi_pll@fd922A00 { compatible = "qcom,mdss_dsi_pll_8974"; label = "MDSS DSI 0 PLL"; cell-index = <0>; reg = <0xfd922A00 0xD4>, <0xfd922900 0x64>, <0xfd8c2300 0x8>; reg-names = "pll_base", "dynamic_pll_base", "gdsc_base"; gdsc-supply = <&gdsc_mdss>; vddio-supply = <&pm8941_l12>; vcca-supply = <&pm8941_l28>; clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, <&clock_gcc clk_gcc_mdss_ahb_clk>, <&clock_gcc clk_gcc_mdss_axi_clk>; clock-names = "mdp_core_clk", "iface_clk", "bus_clk"; clock-rate = <0>, <0>, <0>; qcom,dsi-pll-slave; qcom,dsi-pll-ssc-en; qcom,dsi-pll-ssc-mode = "down-spread"; qcom,ssc-frequency-hz = <30000>; qcom,ssc-ppm = <5000>; qcom,platform-supply-entries { #address-cells = <1>; #size-cells = <0>; qcom,platform-supply-entry@0 { reg = <0>; qcom,supply-name = "vddio"; qcom,supply-min-voltage = <1800000>; qcom,supply-max-voltage = <1800000>; qcom,supply-enable-load = <100000>; qcom,supply-disable-load = <100>; qcom,supply-pre-on-sleep = <0>; qcom,supply-post-on-sleep = <20>; qcom,supply-pre-off-sleep = <0>; qcom,supply-post-off-sleep = <0>; }; }; };
bindings/sde-dsi.txt +13 −3 Original line number Diff line number Diff line Loading @@ -3,17 +3,18 @@ Qualcomm Technologies, Inc. mdss-dsi is the master DSI device which supports multiple DSI host controllers that are compatible with MIPI display serial interface specification. DSI Controller: DSI Controller and PHY: Required properties: - compatible: Should be "qcom,dsi-ctrl-hw-v<version>". Supported versions include 1.4, 2.0 and 2.2. eg: qcom,dsi-ctrl-hw-v1.4, qcom,dsi-ctrl-hw-v2.0, qcom,dsi-ctrl-hw-v2.2, qcom,dsi-ctrl-hw-v2.3, qcom,dsi-ctrl-hw-v2.4 qcom,dsi-ctrl-hw-v2.4, qcom,dsi-ctrl-hw-v2.5 And for dsi phy driver: qcom,dsi-phy-v0.0-hpm, qcom,dsi-phy-v0.0-lpm, qcom,dsi-phy-v1.0, qcom,dsi-phy-v2.0, qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1 qcom,dsi-phy-v3.0, qcom,dsi-phy-v4.0, qcom,dsi-phy-v4.1, qcom,dsi-phy-v4.2 - reg: Base address and length of DSI controller's memory mapped regions. - reg-names: A list of strings that name the list of regs. Loading @@ -32,6 +33,8 @@ Required properties: "core_clk" "byte_clk_rcg" "pixel_clk_rcg" - pll-label Supported versions of DSI PLL: dsi_pll_5nm - gdsc-supply: phandle to gdsc regulator node. - vdda-supply: phandle to vdda regulator node. - vcca-supply: phandle to vcca regulator node. Loading Loading @@ -116,3 +119,10 @@ Optional properties: specified in Documentation/devicetree/bindings/graph.txt. Video port 0 reg 0 is for the bridge output. The remote endpoint phandle should be mipi_dsi_device device node. - qcom,dsi-pll-ssc-en: Boolean property to indicate that ssc is enabled. - qcom,dsi-pll-ssc-mode: Spread-spectrum clocking. It can be either "down-spread" or "center-spread". Default is "down-spread" if it is not specified. - qcom,ssc-frequency-hz: Integer property to specify the spread frequency to be programmed for the SSC. - qcom,ssc-ppm: Integer property to specify the Parts per Million value of SSC.
