Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 5baa22c5 authored by Zhi Wang's avatar Zhi Wang Committed by Daniel Vetter
Browse files

drm/i915: Introduce bit definitions of CTXT_SR_CTRL register. 



This patch introduces 2 bit definitions of context save/restore
control register.

Signed-off-by: default avatarZhi Wang <zhi.a.wang@intel.com>
Suggested-by: default avatarDave Gordon <david.s.gordon@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 25bab385

drivers/gpu/drm/i915/intel_lrc.c

+2 −1
Original line number Diff line number Diff line
@@ -1666,7 +1666,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o 
	reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED;

	reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring);

	reg_state[CTX_CONTEXT_CONTROL+1] =

			_MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);

		_MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |

				CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);

	reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base);

	reg_state[CTX_RING_HEAD+1] = 0;

	reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base);

drivers/gpu/drm/i915/intel_lrc.h

+2 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ 
#define RING_ELSP(ring)			((ring)->mmio_base+0x230)

#define RING_EXECLIST_STATUS(ring)	((ring)->mmio_base+0x234)

#define RING_CONTEXT_CONTROL(ring)	((ring)->mmio_base+0x244)

#define	  CTX_CTRL_INHIBIT_SYN_CTX_SWITCH	(1 << 3)

#define	  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT	(1 << 0)

#define RING_CONTEXT_STATUS_BUF(ring)	((ring)->mmio_base+0x370)

#define RING_CONTEXT_STATUS_PTR(ring)	((ring)->mmio_base+0x3a0)