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Commit 5b799840 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Linus Walleij
Browse files

arm: dts: ste: Update coresight bindings for hardware port 



Switch to the new coresight bindings

Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: default avatarSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 2f967f9e

arch/arm/boot/dts/ste-dbx5x0.dtsi

+33 −32
Original line number Diff line number Diff line
@@ -72,12 +72,14 @@ 
			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU0>;

			out-ports {

				port {

					ptm0_out_port: endpoint {

						remote-endpoint = <&funnel_in_port0>;

					};

				};

			};

		};



		ptm@801af000 {

			compatible = "arm,coresight-etm3x", "arm,primecell";
@@ -86,12 +88,14 @@ 
			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			cpu = <&CPU1>;

			out-ports {

				port {

					ptm1_out_port: endpoint {

						remote-endpoint = <&funnel_in_port1>;

					};

				};

			};

		};



		funnel@801a6000 {

			compatible = "arm,coresight-funnel", "arm,primecell";
@@ -99,32 +103,29 @@ 


			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			ports {

				#address-cells = <1>;

				#size-cells = <0>;



				/* funnel output ports */

				port@0 {

					reg = <0>;

			out-ports {

				port {

					funnel_out_port: endpoint {

						remote-endpoint =

							<&replicator_in_port0>;

					};

				};

			};



				/* funnel input ports */

				port@1 {

			in-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				port@0 {

					reg = <0>;

					funnel_in_port0: endpoint {

						slave-mode;

						remote-endpoint = <&ptm0_out_port>;

					};

				};



				port@2 {

				port@1 {

					reg = <1>;

					funnel_in_port1: endpoint {

						slave-mode;

						remote-endpoint = <&ptm1_out_port>;

					};

				};
@@ -136,11 +137,10 @@ 
			clocks = <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "atclk";



			ports {

			out-ports {

				#address-cells = <1>;

				#size-cells = <0>;



				/* replicator output ports */

				port@0 {

					reg = <0>;

					replicator_out_port0: endpoint {
@@ -153,12 +153,11 @@ 
						remote-endpoint = <&etb_in_port>;

					};

				};

			};



				/* replicator input port */

				port@2 {

					reg = <0>;

			in-ports {

				port {

					replicator_in_port0: endpoint {

						slave-mode;

						remote-endpoint = <&funnel_out_port>;

					};

				};
@@ -171,13 +170,14 @@ 


			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			in-ports {

				port {

					tpiu_in_port: endpoint {

					slave-mode;

						remote-endpoint = <&replicator_out_port0>;

					};

				};

			};

		};



		etb@801a4000 {

			compatible = "arm,coresight-etb10", "arm,primecell";
@@ -185,13 +185,14 @@ 


			clocks = <&prcmu_clk PRCMU_APETRACECLK>, <&prcmu_clk PRCMU_APEATCLK>;

			clock-names = "apb_pclk", "atclk";

			in-ports {

				port {

					etb_in_port: endpoint {

					slave-mode;

						remote-endpoint = <&replicator_out_port1>;

					};

				};

			};

		};



		intc: interrupt-controller@a0411000 {

			compatible = "arm,cortex-a9-gic";