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Commit 5b6eefd6 authored by Manasi Navare's avatar Manasi Navare Committed by Jani Nikula
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drm/i915/dp: Fix DSC enable code to use cpu_transcoder instead of encoder->type 



This patch fixes the intel_configure_pps_for_dsc_encoder() function to use
cpu_transcoder instead of encoder->type to select the correct DSC registers
that was wrongly used in the original patch for one DSC register isntance.

Fixes: 7182414e ("drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling")
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: <stable@vger.kernel.org> # v5.0+
Signed-off-by: default avatarManasi Navare <manasi.d.navare@intel.com>
Reviewed-by: default avatarMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190821215950.24223-1-manasi.d.navare@intel.com


(cherry picked from commit d4c61c4a16decd8ace8660f22c81609a539fccba)
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parent 0a3dfbb5

drivers/gpu/drm/i915/display/intel_vdsc.c

+1 −1
Original line number Diff line number Diff line
@@ -541,7 +541,7 @@ static void intel_configure_pps_for_dsc_encoder(struct intel_encoder *encoder, 
	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |

		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);

	DRM_INFO("PPS2 = 0x%08x\n", pps_val);

	if (encoder->type == INTEL_OUTPUT_EDP) {

	if (cpu_transcoder == TRANSCODER_EDP) {

		I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val);

		/*

		 * If 2 VDSC instances are needed, configure PPS for second