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Commit 5b3f757a authored by Can Guo's avatar Can Guo Committed by Todd Kjos
Browse files

UPSTREAM: scsi: ufs-qcom: Add reset control support for host controller 

Add reset control for host controller so that host controller can be reset
as required in its power up sequence.

Link: https://lore.kernel.org/r/1573798172-20534-3-git-send-email-cang@codeaurora.org


Reviewed-by: default avatarAvri Altman <avri.altman@wdc.com>
Signed-off-by: default avatarCan Guo <cang@codeaurora.org>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>

Bug: 143632303
Change-Id: I92e3c0ea0293603e5aa75566dda98b41fa1978be
(cherry picked from commit 870b1279c7a0344c99d85a9cb1619f6023e752ed)
Signed-off-by: default avatarCan Guo <cang@codeaurora.org>
parent d1a7ad3b

drivers/scsi/ufs/ufs-qcom.c

+53 −0
Original line number Diff line number Diff line
@@ -245,6 +245,44 @@ static void ufs_qcom_select_unipro_mode(struct ufs_qcom_host *host) 
	mb();

}



/**

 * ufs_qcom_host_reset - reset host controller and PHY

 */

static int ufs_qcom_host_reset(struct ufs_hba *hba)

{

	int ret = 0;

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);



	if (!host->core_reset) {

		dev_warn(hba->dev, "%s: reset control not set\n", __func__);

		goto out;

	}



	ret = reset_control_assert(host->core_reset);

	if (ret) {

		dev_err(hba->dev, "%s: core_reset assert failed, err = %d\n",

				 __func__, ret);

		goto out;

	}



	/*

	 * The hardware requirement for delay between assert/deassert

	 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to

	 * ~125us (4/32768). To be on the safe side add 200us delay.

	 */

	usleep_range(200, 210);



	ret = reset_control_deassert(host->core_reset);

	if (ret)

		dev_err(hba->dev, "%s: core_reset deassert failed, err = %d\n",

				 __func__, ret);



	usleep_range(1000, 1100);



out:

	return ret;

}



static int ufs_qcom_power_up_sequence(struct ufs_hba *hba)

{

	struct ufs_qcom_host *host = ufshcd_get_variant(hba);
@@ -253,6 +291,12 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) 
	bool is_rate_B = (UFS_QCOM_LIMIT_HS_RATE == PA_HS_MODE_B)

							? true : false;



	/* Reset UFS Host Controller and PHY */

	ret = ufs_qcom_host_reset(hba);

	if (ret)

		dev_warn(hba->dev, "%s: host reset returned %d\n",

				  __func__, ret);



	if (is_rate_B)

		phy_set_mode(phy, PHY_MODE_UFS_HS_B);
@@ -1168,6 +1212,15 @@ static int ufs_qcom_init(struct ufs_hba *hba) 
	host->hba = hba;

	ufshcd_set_variant(hba, host);



	/* Setup the reset control of HCI */

	host->core_reset = devm_reset_control_get(hba->dev, "rst");

	if (IS_ERR(host->core_reset)) {

		err = PTR_ERR(host->core_reset);

		dev_warn(dev, "Failed to get reset control %d\n", err);

		host->core_reset = NULL;

		err = 0;

	}



	/* Fire up the reset controller. Failure here is non-fatal. */

	host->rcdev.of_node = dev->of_node;

	host->rcdev.ops = &ufs_qcom_reset_ops;

drivers/scsi/ufs/ufs-qcom.h

+3 −0
Original line number Diff line number Diff line
@@ -6,6 +6,7 @@ 
#define UFS_QCOM_H_



#include <linux/reset-controller.h>

#include <linux/reset.h>



#define MAX_UFS_QCOM_HOSTS	1

#define MAX_U32                 (~(u32)0)
@@ -233,6 +234,8 @@ struct ufs_qcom_host { 
	u32 dbg_print_en;

	struct ufs_qcom_testbus testbus;



	/* Reset control of HCI */

	struct reset_control *core_reset;

	struct reset_controller_dev rcdev;



	struct gpio_desc *device_reset;