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Commit 5ade2c2f authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter
Browse files

drm/i915: wait for IPS_ENABLE when enabling IPS 



At the end of haswell_crtc_enable we have an intel_wait_for_vblank
with a big comment, and the message suggests it's a workaround for
something we don't really understand. So I removed that wait and
started getting HW state readout error messages saying that the IPS
state is not what we expected.

I investigated and concluded that after you write IPS_ENABLE to
IPS_CTL, the bit will only actually become 1 on the next vblank. So
add code to wait for the IPS_ENABLE bit. We don't really need this
wait right now due to the wait I already mentioned, but at least this
one has a reason to be there, while the other one is just to
workaround some problem: we may remove it in the future.

The wait also acts as a POSTING_READ which we missed.

Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 076e29f2

drivers/gpu/drm/i915/intel_display.c

+8 −0
Original line number Diff line number Diff line
@@ -3346,6 +3346,14 @@ void hsw_enable_ips(struct intel_crtc *crtc) 
	 * for a vblank, so all we need to do here is to enable the IPS bit. */

	assert_plane_enabled(dev_priv, crtc->plane);

	I915_WRITE(IPS_CTL, IPS_ENABLE);



	/* The bit only becomes 1 in the next vblank, so this wait here is

	 * essentially intel_wait_for_vblank. If we don't have this and don't

	 * wait for vblanks until the end of crtc_enable, then the HW state

	 * readout code will complain that the expected IPS_CTL value is not the

	 * one we read. */

	if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))

		DRM_ERROR("Timed out waiting for IPS enable\n");

}



void hsw_disable_ips(struct intel_crtc *crtc)