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Commit 5a9fc531 authored by Brian Masney's avatar Brian Masney Committed by Bjorn Andersson
Browse files

ARM: dts: msm8974: add display support 



Add the MDP5, DSI and DSI PHY blocks for the display found on the
msm8974 SoCs. This is based on work from msm8916.dtsi and Jonathan
Marek.

Signed-off-by: default avatarBrian Masney <masneyb@onstation.org>
Reviewed-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
parent 030b6d48

arch/arm/boot/dts/qcom-msm8974.dtsi

+132 −0
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 


#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,gcc-msm8974.h>

#include <dt-bindings/clock/qcom,mmcc-msm8974.h>

#include <dt-bindings/clock/qcom,rpmcc.h>

#include <dt-bindings/reset/qcom,gcc-msm8974.h>

#include <dt-bindings/gpio/gpio.h>
@@ -1085,6 +1086,137 @@ 
				};

			};

		};



		mdss: mdss@fd900000 {

			status = "disabled";



			compatible = "qcom,mdss";

			reg = <0xfd900000 0x100>,

			      <0xfd924000 0x1000>;

			reg-names = "mdss_phys",

			            "vbif_phys";



			power-domains = <&mmcc MDSS_GDSC>;



			clocks = <&mmcc MDSS_AHB_CLK>,

			         <&mmcc MDSS_AXI_CLK>,

			         <&mmcc MDSS_VSYNC_CLK>;

			clock-names = "iface",

			              "bus",

			              "vsync";



			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;



			interrupt-controller;

			#interrupt-cells = <1>;



			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			mdp: mdp@fd900000 {

				status = "disabled";



				compatible = "qcom,mdp5";

				reg = <0xfd900100 0x22000>;

				reg-names = "mdp_phys";



				interrupt-parent = <&mdss>;

				interrupts = <0 0>;



				clocks = <&mmcc MDSS_AHB_CLK>,

					 <&mmcc MDSS_AXI_CLK>,

					 <&mmcc MDSS_MDP_CLK>,

					 <&mmcc MDSS_VSYNC_CLK>;

				clock-names = "iface",

				              "bus",

				              "core",

				              "vsync";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						mdp5_intf1_out: endpoint {

							remote-endpoint = <&dsi0_in>;

						};

					};

				};

			};



			dsi0: dsi@fd922800 {

				status = "disabled";



				compatible = "qcom,mdss-dsi-ctrl";

				reg = <0xfd922800 0x1f8>;

				reg-names = "dsi_ctrl";



				interrupt-parent = <&mdss>;

				interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;



				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,

				                  <&mmcc PCLK0_CLK_SRC>;

				assigned-clock-parents = <&dsi_phy0 0>,

				                         <&dsi_phy0 1>;



				clocks = <&mmcc MDSS_MDP_CLK>,

				         <&mmcc MDSS_AHB_CLK>,

				         <&mmcc MDSS_AXI_CLK>,

				         <&mmcc MDSS_BYTE0_CLK>,

				         <&mmcc MDSS_PCLK0_CLK>,

				         <&mmcc MDSS_ESC0_CLK>,

				         <&mmcc MMSS_MISC_AHB_CLK>;

				clock-names = "mdp_core",

				              "iface",

				              "bus",

				              "byte",

				              "pixel",

				              "core",

				              "core_mmss";



				phys = <&dsi_phy0>;

				phy-names = "dsi-phy";



				ports {

					#address-cells = <1>;

					#size-cells = <0>;



					port@0 {

						reg = <0>;

						dsi0_in: endpoint {

							remote-endpoint = <&mdp5_intf1_out>;

						};

					};



					port@1 {

						reg = <1>;

						dsi0_out: endpoint {

						};

					};

				};

			};



			dsi_phy0: dsi-phy@fd922a00 {

				status = "disabled";



				compatible = "qcom,dsi-phy-28nm-hpm";

				reg = <0xfd922a00 0xd4>,

				      <0xfd922b00 0x280>,

				      <0xfd922d80 0x30>;

				reg-names = "dsi_pll",

				            "dsi_phy",

				            "dsi_phy_regulator";



				#clock-cells = <1>;

				#phy-cells = <0>;

				qcom,dsi-phy-index = <0>;



				clocks = <&mmcc MDSS_AHB_CLK>;

				clock-names = "iface";

			};

		};

	};



	smd {