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Commit 5a8e0343 authored by Akshay Chandrashekhar Kalghatgi's avatar Akshay Chandrashekhar Kalghatgi
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ARM: dts: msm: vidc: Add register value mask 

Add a register value mask which will specify which bits of the register
will be updated with the value. For instance, if mask is 0x11, then
only bit 0 & bit 4 will be updated with the corresponding bits of the
specified value.

Change-Id: I27471c3afee72ac99f955030ab2100f3685d46d9
parent 91ceb262

qcom/lahaina-vidc.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -32,7 +32,7 @@ 
			<&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>;

		reset-names = "video_axi_reset", "video_core_reset";



		qcom,reg-presets = <0xB0088 0x0>;

		qcom,reg-presets = <0xB0088 0x0 0x11>;



		/* Bus Interconnects */

		interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";