Merge "clk: qcom: Add enable/disable to clk_regmap_mux_div_ops"

	return 0;

}

static int mux_div_enable(struct clk_hw *hw)

{

	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);

	return mux_div_set_src_div(md, md->src, md->div);

}

static void mux_div_disable(struct clk_hw *hw)

{

	struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);

	mux_div_set_src_div(md, md->safe_src, md->safe_div);

}

const struct clk_ops clk_regmap_mux_div_ops = {

	.enable = mux_div_enable,

	.disable = mux_div_disable,

	.get_parent = mux_div_get_parent,

	.set_parent = mux_div_set_parent,

	.set_rate = mux_div_set_rate,

 * @src_shift:	lowest bit of source select field

 * @div:	the divider raw configuration value

 * @src:	the mux index which will be used if the clock is enabled

 * @safe_src:	the safe source mux value we switch to, while the main PLL is

 *		reconfigured

 * @safe_div:	the safe divider value that we set, while the main PLL is

 *		reconfigured

 * @safe_freq:	When switching rates from A to B, the mux div clock will

 *		instead switch from A -> safe_freq -> B. This allows the

 *		mux_div clock to change rates while enabled, even if this

 *		behavior is not supported by the parent clocks.

 *		If changing the rate of parent A also causes the rate of

 *		parent B to change, then safe_freq must be defined.

 *		safe_freq is expected to have a source clock which is always

 *		on and runs at only one rate.

 * @parent_map: pointer to parent_map struct

 * @clkr:	handle between common and hardware-specific interfaces

 * @pclk:	the input PLL clock

	u32				src_shift;

	u32				div;

	u32				src;

	u32				safe_src;

	u32				safe_div;

	unsigned long			safe_freq;

	const struct parent_map		*parent_map;

	struct clk_regmap		clkr;

	struct clk			*pclk;