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Commit 5a25b6f5 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman
Browse files

powerpc/mm: Make MMU_FTR_RADIX a MMU family feature 



MMU feature bits are defined such that we use the lower half to
present MMU family features. Remove the strict split of half and
also move Radix to a mmu family feature. Radix introduce a new MMU
model and strictly speaking it is a new MMU family. This also free
up bits which can be used for individual features later.

Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent a28e46f1

arch/powerpc/include/asm/book3s/64/mmu.h

+1 −1
Original line number Diff line number Diff line
@@ -24,7 +24,7 @@ struct mmu_psize_def { 
extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];



#ifdef CONFIG_PPC_RADIX_MMU

#define radix_enabled() mmu_has_feature(MMU_FTR_RADIX)

#define radix_enabled() mmu_has_feature(MMU_FTR_TYPE_RADIX)

#else

#define radix_enabled() (0)

#endif

arch/powerpc/include/asm/mmu.h

+7 −8
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
 */



/*

 * First half is MMU families

 * MMU families

 */

#define MMU_FTR_HPTE_TABLE		ASM_CONST(0x00000001)

#define MMU_FTR_TYPE_8xx		ASM_CONST(0x00000002)
@@ -21,9 +21,13 @@ 
#define MMU_FTR_TYPE_FSL_E		ASM_CONST(0x00000010)

#define MMU_FTR_TYPE_47x		ASM_CONST(0x00000020)



/* Radix page table supported and enabled */

#define MMU_FTR_TYPE_RADIX		ASM_CONST(0x00000040)



/*

 * This is individual features

 * Individual features below.

 */



/*

 * We need to clear top 16bits of va (from the remaining 64 bits )in

 * tlbie* instructions
@@ -93,11 +97,6 @@ 
 */

#define MMU_FTR_1T_SEGMENT		ASM_CONST(0x40000000)



/*

 * Radix page table available

 */

#define MMU_FTR_RADIX			ASM_CONST(0x80000000)



/* MMU feature bit sets for various CPUs */

#define MMU_FTRS_DEFAULT_HPTE_ARCH_V2	\

	MMU_FTR_HPTE_TABLE | MMU_FTR_PPCAS_ARCH_V2
@@ -131,7 +130,7 @@ enum { 
		MMU_FTR_LOCKLESS_TLBIE | MMU_FTR_CI_LARGE_PAGE |

		MMU_FTR_1T_SEGMENT | MMU_FTR_TLBIE_CROP_VA |

#ifdef CONFIG_PPC_RADIX_MMU

		MMU_FTR_RADIX |

		MMU_FTR_TYPE_RADIX |

#endif

		0,

};

arch/powerpc/kernel/entry_64.S

+1 −1
Original line number Diff line number Diff line
@@ -532,7 +532,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300) 
#ifdef CONFIG_PPC_STD_MMU_64

BEGIN_MMU_FTR_SECTION

	b	2f

END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)

END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)

BEGIN_FTR_SECTION

	clrrdi	r6,r8,28	/* get its ESID */

	clrrdi	r9,r1,28	/* get current sp ESID */

arch/powerpc/kernel/exceptions-64s.S

+4 −4
Original line number Diff line number Diff line
@@ -938,7 +938,7 @@ BEGIN_MMU_FTR_SECTION 
	b	do_hash_page		/* Try to handle as hpte fault */

MMU_FTR_SECTION_ELSE

	b	handle_page_fault

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)



	.align  7

	.globl  h_data_storage_common
@@ -969,7 +969,7 @@ BEGIN_MMU_FTR_SECTION 
	b	do_hash_page		/* Try to handle as hpte fault */

MMU_FTR_SECTION_ELSE

	b	handle_page_fault

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)



	STD_EXCEPTION_COMMON(0xe20, h_instr_storage, unknown_exception)
@@ -1390,7 +1390,7 @@ slb_miss_realmode: 
#ifdef CONFIG_PPC_STD_MMU_64

BEGIN_MMU_FTR_SECTION

	bl	slb_allocate_realmode

END_MMU_FTR_SECTION_IFCLR(MMU_FTR_RADIX)

END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)

#endif

	/* All done -- return from exception. */
@@ -1404,7 +1404,7 @@ BEGIN_MMU_FTR_SECTION 
	beq-	2f

FTR_SECTION_ELSE

	b	2f

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_RADIX)

ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)



.machine	push

.machine	"power4"

arch/powerpc/kernel/idle_book3s.S

+1 −1
Original line number Diff line number Diff line
@@ -570,7 +570,7 @@ common_exit: 


BEGIN_MMU_FTR_SECTION

	b	no_segments

END_MMU_FTR_SECTION_IFSET(MMU_FTR_RADIX)

END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)

	/* Restore SLB  from PACA */

	ld	r8,PACA_SLBSHADOWPTR(r13)