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Commit 59caeaee authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge branch 'linux-4.0' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes 

nouveau fixes, and gm206 modesetting enables.

* 'linux-4.0' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nouveau/bios: fix i2c table parsing for dcb 4.1
  drm/nouveau/device/gm100: Basic GM206 bring up (as copy of GM204)
  drm/nouveau/device: post write to NV_PMC_BOOT_1 when flipping endian switch
  drm/nouveau/gr/gf100: fix some accidental or'ing of buffer addresses
  drm/nouveau/fifo/nv04: remove the loop from the interrupt handler
parents 06e5801b 5a6f690c

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+4 −2
Original line number Diff line number Diff line
@@ -340,11 +340,13 @@ nvkm_devobj_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 


		/* switch mmio to cpu's native endianness */

#ifndef __BIG_ENDIAN

		if (ioread32_native(map + 0x000004) != 0x00000000)

		if (ioread32_native(map + 0x000004) != 0x00000000) {

#else

		if (ioread32_native(map + 0x000004) == 0x00000000)

		if (ioread32_native(map + 0x000004) == 0x00000000) {

#endif

			iowrite32_native(0x01000001, map + 0x000004);

			ioread32_native(map);

		}



		/* read boot0 and strapping information */

		boot0 = ioread32_native(map + 0x000000);

drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c

+43 −0
Original line number Diff line number Diff line
@@ -140,6 +140,49 @@ gm100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;

#endif

		break;

	case 0x126:

		device->cname = "GM206";

		device->oclass[NVDEV_SUBDEV_VBIOS  ] = &nvkm_bios_oclass;

		device->oclass[NVDEV_SUBDEV_GPIO   ] =  gk104_gpio_oclass;

		device->oclass[NVDEV_SUBDEV_I2C    ] =  gm204_i2c_oclass;

		device->oclass[NVDEV_SUBDEV_FUSE   ] = &gm107_fuse_oclass;

#if 0

		/* looks to be some non-trivial changes */

		device->oclass[NVDEV_SUBDEV_CLK    ] = &gk104_clk_oclass;

		/* priv ring says no to 0x10eb14 writes */

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gm107_therm_oclass;

#endif

		device->oclass[NVDEV_SUBDEV_MXM    ] = &nv50_mxm_oclass;

		device->oclass[NVDEV_SUBDEV_DEVINIT] =  gm204_devinit_oclass;

		device->oclass[NVDEV_SUBDEV_MC     ] =  gk20a_mc_oclass;

		device->oclass[NVDEV_SUBDEV_BUS    ] =  gf100_bus_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &gk20a_timer_oclass;

		device->oclass[NVDEV_SUBDEV_FB     ] =  gm107_fb_oclass;

		device->oclass[NVDEV_SUBDEV_LTC    ] =  gm107_ltc_oclass;

		device->oclass[NVDEV_SUBDEV_IBUS   ] = &gk104_ibus_oclass;

		device->oclass[NVDEV_SUBDEV_INSTMEM] =  nv50_instmem_oclass;

		device->oclass[NVDEV_SUBDEV_MMU    ] = &gf100_mmu_oclass;

		device->oclass[NVDEV_SUBDEV_BAR    ] = &gf100_bar_oclass;

		device->oclass[NVDEV_SUBDEV_PMU    ] =  gk208_pmu_oclass;

#if 0

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

#endif

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

#if 0

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gk208_fifo_oclass;

		device->oclass[NVDEV_ENGINE_SW     ] =  gf100_sw_oclass;

		device->oclass[NVDEV_ENGINE_GR     ] =  gm107_gr_oclass;

#endif

		device->oclass[NVDEV_ENGINE_DISP   ] =  gm204_disp_oclass;

#if 0

		device->oclass[NVDEV_ENGINE_CE0    ] = &gm204_ce0_oclass;

		device->oclass[NVDEV_ENGINE_CE1    ] = &gm204_ce1_oclass;

		device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;

		device->oclass[NVDEV_ENGINE_MSVLD  ] = &gk104_msvld_oclass;

		device->oclass[NVDEV_ENGINE_MSPDEC ] = &gk104_mspdec_oclass;

		device->oclass[NVDEV_ENGINE_MSPPP  ] = &gf100_msppp_oclass;

#endif

		break;

	default:

drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c

+35 −50
Original line number Diff line number Diff line
@@ -502,34 +502,29 @@ nv04_fifo_intr(struct nvkm_subdev *subdev) 
{

	struct nvkm_device *device = nv_device(subdev);

	struct nv04_fifo_priv *priv = (void *)subdev;

	uint32_t status, reassign;

	int cnt = 0;

	u32 mask = nv_rd32(priv, NV03_PFIFO_INTR_EN_0);

	u32 stat = nv_rd32(priv, NV03_PFIFO_INTR_0) & mask;

	u32 reassign, chid, get, sem;



	reassign = nv_rd32(priv, NV03_PFIFO_CACHES) & 1;

	while ((status = nv_rd32(priv, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {

		uint32_t chid, get;



	nv_wr32(priv, NV03_PFIFO_CACHES, 0);



	chid = nv_rd32(priv, NV03_PFIFO_CACHE1_PUSH1) & priv->base.max;

	get  = nv_rd32(priv, NV03_PFIFO_CACHE1_GET);



		if (status & NV_PFIFO_INTR_CACHE_ERROR) {

	if (stat & NV_PFIFO_INTR_CACHE_ERROR) {

		nv04_fifo_cache_error(device, priv, chid, get);

			status &= ~NV_PFIFO_INTR_CACHE_ERROR;

		stat &= ~NV_PFIFO_INTR_CACHE_ERROR;

	}



		if (status & NV_PFIFO_INTR_DMA_PUSHER) {

	if (stat & NV_PFIFO_INTR_DMA_PUSHER) {

		nv04_fifo_dma_pusher(device, priv, chid);

			status &= ~NV_PFIFO_INTR_DMA_PUSHER;

		stat &= ~NV_PFIFO_INTR_DMA_PUSHER;

	}



		if (status & NV_PFIFO_INTR_SEMAPHORE) {

			uint32_t sem;



			status &= ~NV_PFIFO_INTR_SEMAPHORE;

			nv_wr32(priv, NV03_PFIFO_INTR_0,

				NV_PFIFO_INTR_SEMAPHORE);

	if (stat & NV_PFIFO_INTR_SEMAPHORE) {

		stat &= ~NV_PFIFO_INTR_SEMAPHORE;

		nv_wr32(priv, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE);



		sem = nv_rd32(priv, NV10_PFIFO_CACHE1_SEMAPHORE);

		nv_wr32(priv, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
@@ -539,37 +534,27 @@ nv04_fifo_intr(struct nvkm_subdev *subdev) 
	}



	if (device->card_type == NV_50) {

			if (status & 0x00000010) {

				status &= ~0x00000010;

		if (stat & 0x00000010) {

			stat &= ~0x00000010;

			nv_wr32(priv, 0x002100, 0x00000010);

		}



			if (status & 0x40000000) {

		if (stat & 0x40000000) {

			nv_wr32(priv, 0x002100, 0x40000000);

			nvkm_fifo_uevent(&priv->base);

				status &= ~0x40000000;

			stat &= ~0x40000000;

		}

	}



		if (status) {

			nv_warn(priv, "unknown intr 0x%08x, ch %d\n",

				status, chid);

			nv_wr32(priv, NV03_PFIFO_INTR_0, status);

			status = 0;

	if (stat) {

		nv_warn(priv, "unknown intr 0x%08x\n", stat);

		nv_mask(priv, NV03_PFIFO_INTR_EN_0, stat, 0x00000000);

		nv_wr32(priv, NV03_PFIFO_INTR_0, stat);

	}



	nv_wr32(priv, NV03_PFIFO_CACHES, reassign);

}



	if (status) {

		nv_error(priv, "still angry after %d spins, halt\n", cnt);

		nv_wr32(priv, 0x002140, 0);

		nv_wr32(priv, 0x000140, 0);

	}



	nv_wr32(priv, 0x000100, 0x00000100);

}



static int

nv04_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine,

	       struct nvkm_oclass *oclass, void *data, u32 size,

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.c

+2 −2
Original line number Diff line number Diff line
@@ -1032,9 +1032,9 @@ gf100_grctx_generate_bundle(struct gf100_grctx *info) 
	const int s = 8;

	const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);

	mmio_refn(info, 0x408004, 0x00000000, s, b);

	mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);

	mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s));

	mmio_refn(info, 0x418808, 0x00000000, s, b);

	mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);

	mmio_wr32(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s));

}



void

drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgk104.c

+2 −2
Original line number Diff line number Diff line
@@ -851,9 +851,9 @@ gk104_grctx_generate_bundle(struct gf100_grctx *info) 
	const int s = 8;

	const int b = mmio_vram(info, impl->bundle_size, (1 << s), access);

	mmio_refn(info, 0x408004, 0x00000000, s, b);

	mmio_refn(info, 0x408008, 0x80000000 | (impl->bundle_size >> s), 0, b);

	mmio_wr32(info, 0x408008, 0x80000000 | (impl->bundle_size >> s));

	mmio_refn(info, 0x418808, 0x00000000, s, b);

	mmio_refn(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s), 0, b);

	mmio_wr32(info, 0x41880c, 0x80000000 | (impl->bundle_size >> s));

	mmio_wr32(info, 0x4064c8, (state_limit << 16) | token_limit);

}