dt-bindings: display: sunxi-drm: Add TCON TOP description

   - 'lvds-alt': An alternative clock source, separate from the TCON channel 0

                 clock, that can be used to drive the LVDS clock

TCON TOP

--------

TCON TOPs main purpose is to configure whole display pipeline. It determines

relationships between mixers and TCONs, selects source TCON for HDMI, muxes

LCD and TV encoder GPIO output, selects TV encoder clock source and contains

additional TV TCON and DSI gates.

It allows display pipeline to be configured in very different ways:

                                / LCD0/LVDS0

                 / [0] TCON-LCD0

                 |              \ MIPI DSI

 mixer0          |

        \        / [1] TCON-LCD1 - LCD1/LVDS1

         TCON-TOP

        /        \ [2] TCON-TV0 [0] - TVE0/RGB

 mixer1          |                  \

                 |                   TCON-TOP - HDMI

                 |                  /

                 \ [3] TCON-TV1 [1] - TVE1/RGB

Note that both TCON TOP references same physical unit. Both mixers can be

connected to any TCON.

Required properties:

  - compatible: value must be one of:

    * allwinner,sun8i-r40-tcon-top

  - reg: base address and size of the memory-mapped region.

  - clocks: phandle to the clocks feeding the TCON TOP

    * bus: TCON TOP interface clock

    * tcon-tv0: TCON TV0 clock

    * tve0: TVE0 clock

    * tcon-tv1: TCON TV1 clock

    * tve1: TVE0 clock

    * dsi: MIPI DSI clock

  - clock-names: clock name mentioned above

  - resets: phandle to the reset line driving the TCON TOP

  - #clock-cells : must contain 1

  - clock-output-names: Names of clocks created for TCON TV0 channel clock,

    TCON TV1 channel clock and DSI channel clock, in that order.

- ports: A ports node with endpoint definitions as defined in

    Documentation/devicetree/bindings/media/video-interfaces.txt. 6 ports should

    be defined:

    * port 0 is input for mixer0 mux

    * port 1 is output for mixer0 mux

    * port 2 is input for mixer1 mux

    * port 3 is output for mixer1 mux

    * port 4 is input for HDMI mux

    * port 5 is output for HDMI mux

    All output endpoints for mixer muxes and input endpoints for HDMI mux should

    have reg property with the id of the target TCON, as shown in above graph

    (0-3 for mixer muxes and 0-1 for HDMI mux). All ports should have only one

    endpoint connected to remote endpoint.

DRC

---

/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */

/* Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */

#ifndef _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_

#define _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_

#define CLK_TCON_TOP_TV0	0

#define CLK_TCON_TOP_TV1	1

#define CLK_TCON_TOP_DSI	2

#endif /* _DT_BINDINGS_CLOCK_SUN8I_TCON_TOP_H_ */