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Commit 5915838b authored by Geert Uytterhoeven's avatar Geert Uytterhoeven
Browse files

clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment 



PLL0 runs at 4.8 GHz, i.e. EXTAL x 100.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 7c0043c0

drivers/clk/renesas/r8a77990-cpg-mssr.c

+2 −2
Original line number Diff line number Diff line
@@ -250,8 +250,8 @@ static const unsigned int r8a77990_crit_mod_clks[] __initconst = { 
/*

 * MD19		EXTAL (MHz)	PLL0		PLL1		PLL3

 *--------------------------------------------------------------------

 * 0		48 x 1		x100/4		x100/3		x100/3

 * 1		48 x 1		x100/4		x100/3		 x58/3

 * 0		48 x 1		x100/1		x100/3		x100/3

 * 1		48 x 1		x100/1		x100/3		 x58/3

 */

#define CPG_PLL_CONFIG_INDEX(md)	(((md) & BIT(19)) >> 19)