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Commit 590627f7 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf tooling fixes from Thomas Gleixner:
 "Core libraries:
   - Fix max perf_event_attr.precise_ip detection.
   - Fix parser error for uncore event alias
   - Fixup ordering of kernel maps after obtaining the main kernel map
     address.

  Intel PT:
   - Fix TSC slip where A TSC packet can slip past MTC packets so that
     the timestamp appears to go backwards.
   - Fixes for exported-sql-viewer GUI conversion to python3.

  ARM coresight:
   - Fix the build by adding a missing case value for enumeration value
     introduced in newer library, that now is the required one.

  tool headers:
   - Syncronize kernel headers with the kernel, getting new io_uring and
     pidfd_send_signal syscalls so that 'perf trace' can handle them"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf pmu: Fix parser error for uncore event alias
  perf scripts python: exported-sql-viewer.py: Fix python3 support
  perf scripts python: exported-sql-viewer.py: Fix never-ending loop
  perf machine: Update kernel map address and re-order properly
  tools headers uapi: Sync powerpc's asm/kvm.h copy with the kernel sources
  tools headers: Update x86's syscall_64.tbl and uapi/asm-generic/unistd
  tools headers uapi: Update drm/i915_drm.h
  tools arch x86: Sync asm/cpufeatures.h with the kernel sources
  tools headers uapi: Sync linux/fcntl.h to get the F_SEAL_FUTURE_WRITE addition
  tools headers uapi: Sync asm-generic/mman-common.h and linux/mman.h
  perf evsel: Fix max perf_event_attr.precise_ip detection
  perf intel-pt: Fix TSC slip
  perf cs-etm: Add missing case value
parents c29d8541 22261fdf

tools/arch/alpha/include/uapi/asm/mman.h

+0 −2
Original line number Diff line number Diff line
@@ -27,8 +27,6 @@ 
#define MAP_NONBLOCK	0x40000

#define MAP_NORESERVE	0x10000

#define MAP_POPULATE	0x20000

#define MAP_PRIVATE	0x02

#define MAP_SHARED	0x01

#define MAP_STACK	0x80000

#define PROT_EXEC	0x4

#define PROT_GROWSDOWN	0x01000000

tools/arch/mips/include/uapi/asm/mman.h

+0 −2
Original line number Diff line number Diff line
@@ -28,8 +28,6 @@ 
#define MAP_NONBLOCK	0x20000

#define MAP_NORESERVE	0x0400

#define MAP_POPULATE	0x10000

#define MAP_PRIVATE	0x002

#define MAP_SHARED	0x001

#define MAP_STACK	0x40000

#define PROT_EXEC	0x04

#define PROT_GROWSDOWN	0x01000000

tools/arch/parisc/include/uapi/asm/mman.h

+0 −2
Original line number Diff line number Diff line
@@ -27,8 +27,6 @@ 
#define MAP_NONBLOCK	0x20000

#define MAP_NORESERVE	0x4000

#define MAP_POPULATE	0x10000

#define MAP_PRIVATE	0x02

#define MAP_SHARED	0x01

#define MAP_STACK	0x40000

#define PROT_EXEC	0x4

#define PROT_GROWSDOWN	0x01000000

tools/arch/powerpc/include/uapi/asm/kvm.h

+2 −0
Original line number Diff line number Diff line
@@ -463,10 +463,12 @@ struct kvm_ppc_cpu_char { 
#define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED	(1ULL << 58)

#define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF	(1ULL << 57)

#define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS	(1ULL << 56)

#define KVM_PPC_CPU_CHAR_BCCTR_FLUSH_ASSIST	(1ull << 54)



#define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY	(1ULL << 63)

#define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR		(1ULL << 62)

#define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR	(1ULL << 61)

#define KVM_PPC_CPU_BEHAV_FLUSH_COUNT_CACHE	(1ull << 58)



/* Per-vcpu XICS interrupt controller state */

#define KVM_REG_PPC_ICP_STATE	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)

tools/arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -344,6 +344,7 @@ 
/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */

#define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */

#define X86_FEATURE_TSX_FORCE_ABORT	(18*32+13) /* "" TSX_FORCE_ABORT */

#define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */