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Unverified Commit 58d1d8f5 authored by Michael Bestas's avatar Michael Bestas
Browse files

Merge tag 'ASB-2024-07-05_11-5.4' of... 

Merge tag 'ASB-2024-07-05_11-5.4' of https://android.googlesource.com/kernel/common into android13-5.4-lahaina

https://source.android.com/docs/security/bulletin/2024-07-01
CVE-2024-26923

* tag 'ASB-2024-07-05_11-5.4' of https://android.googlesource.com/kernel/common: (193 commits)
  ANDROID: fix kernelci build breaks due to hid/uhid cyclic dependency
  UPSTREAM: af_unix: Fix garbage collector racing against connect()
  ANDROID: 16K: Only check basename of linker context
  UPSTREAM: af_unix: Do not use atomic ops for unix_sk(sk)->inflight.
  Linux 5.4.276
  pinctrl: mediatek: paris: Fix PIN_CONFIG_INPUT_SCHMITT_ENABLE readback
  pinctrl: mediatek: remove set but not used variable 'e'
  pinctrl: mediatek: Fix some off by one bugs
  pinctrl: mediatek: Fix fallback behavior for bias_set_combo
  regulator: core: fix debugfs creation regression
  net: fix out-of-bounds access in ops_init
  drm/vmwgfx: Fix invalid reads in fence signaled events
  dyndbg: fix old BUG_ON in >control parser
  tipc: fix UAF in error path
  usb: gadget: f_fs: Fix a race condition when processing setup packets.
  usb: gadget: composite: fix OS descriptors w_value logic
  firewire: nosy: ensure user_length is taken into account when fetching packet contents
  net: qede: use return from qede_parse_flow_attr() for flower
  net: qede: sanitize 'rc' in qede_add_tc_flower_fltr()
  ipv6: fib6_rules: avoid possible NULL dereference in fib6_rule_action()
  ...

 Conflicts:
	net/unix/garbage.c

Change-Id: I9d928b110c82362cd82e7e9cc3bb19c664cdd53d
parents fa50f717 7f5fa807

Makefile

+1 −1
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0

VERSION = 5

PATCHLEVEL = 4

SUBLEVEL = 274

SUBLEVEL = 276

EXTRAVERSION =

NAME = Kleptomaniac Octopus

arch/arc/boot/dts/hsdk.dts

+0 −1
Original line number Diff line number Diff line
@@ -205,7 +205,6 @@ 
		};



		gmac: ethernet@8000 {

			#interrupt-cells = <1>;

			compatible = "snps,dwmac";

			reg = <0x8000 0x2000>;

			interrupts = <10>;

arch/arm64/boot/dts/mediatek/mt2712-evb.dts

+76 −2
Original line number Diff line number Diff line
@@ -105,15 +105,89 @@ 
	proc-supply = <&cpus_fixed_vproc1>;

};



&eth {

	phy-mode ="rgmii-rxid";

	phy-handle = <&ethernet_phy0>;

	mediatek,tx-delay-ps = <1530>;

	snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;

	pinctrl-names = "default", "sleep";

	pinctrl-0 = <&eth_default>;

	pinctrl-1 = <&eth_sleep>;

	status = "okay";



	mdio {

		compatible = "snps,dwmac-mdio";

		#address-cells = <1>;

		#size-cells = <0>;

		ethernet_phy0: ethernet-phy@5 {

			compatible = "ethernet-phy-id0243.0d90";

			reg = <0x5>;

		};

	};

};



&pio {

	usb0_id_pins_float: usb0_iddig {

	eth_default: eth-default-pins {

		tx_pins {

			pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,

				 <MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,

				 <MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1>,

				 <MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>,

				 <MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>,

				 <MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>;

			drive-strength = <MTK_DRIVE_8mA>;

		};

		rx_pins {

			pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>,

				 <MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2>,

				 <MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1>,

				 <MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0>,

				 <MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV>,

				 <MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC>;

			input-enable;

		};

		mdio_pins {

			pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>,

				 <MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>;

			drive-strength = <MTK_DRIVE_8mA>;

			input-enable;

		};

	};



	eth_sleep: eth-sleep-pins {

		tx_pins {

			pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,

				 <MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,

				 <MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73>,

				 <MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74>,

				 <MT2712_PIN_75_GBE_TXC__FUNC_GPIO75>,

				 <MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76>;

		};

		rx_pins {

			pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78>,

				 <MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79>,

				 <MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80>,

				 <MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81>,

				 <MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82>,

				 <MT2712_PIN_84_GBE_RXC__FUNC_GPIO84>;

			input-disable;

		};

		mdio_pins {

			pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GPIO85>,

				 <MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86>;

			input-disable;

			bias-disable;

		};

	};



	usb0_id_pins_float: usb0-iddig-pins {

		pins_iddig {

			pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;

			bias-pull-up;

		};

	};



	usb1_id_pins_float: usb1_iddig {

	usb1_id_pins_float: usb1-iddig-pins {

		pins_iddig {

			pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;

			bias-pull-up;

arch/arm64/boot/dts/mediatek/mt2712e.dtsi

+67 −1
Original line number Diff line number Diff line
@@ -249,10 +249,11 @@ 
		#clock-cells = <1>;

	};



	infracfg: syscon@10001000 {

	infracfg: clock-controller@10001000 {

		compatible = "mediatek,mt2712-infracfg", "syscon";

		reg = <0 0x10001000 0 0x1000>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	pericfg: syscon@10003000 {
@@ -632,6 +633,71 @@ 
		status = "disabled";

	};



	stmmac_axi_setup: stmmac-axi-config {

		snps,wr_osr_lmt = <0x7>;

		snps,rd_osr_lmt = <0x7>;

		snps,blen = <0 0 0 0 16 8 4>;

	};



	mtl_rx_setup: rx-queues-config {

		snps,rx-queues-to-use = <1>;

		snps,rx-sched-sp;

		queue0 {

			snps,dcb-algorithm;

			snps,map-to-dma-channel = <0x0>;

			snps,priority = <0x0>;

		};

	};



	mtl_tx_setup: tx-queues-config {

		snps,tx-queues-to-use = <3>;

		snps,tx-sched-wrr;

		queue0 {

			snps,weight = <0x10>;

			snps,dcb-algorithm;

			snps,priority = <0x0>;

		};

		queue1 {

			snps,weight = <0x11>;

			snps,dcb-algorithm;

			snps,priority = <0x1>;

		};

		queue2 {

			snps,weight = <0x12>;

			snps,dcb-algorithm;

			snps,priority = <0x2>;

		};

	};



	eth: ethernet@1101c000 {

		compatible = "mediatek,mt2712-gmac";

		reg = <0 0x1101c000 0 0x1300>;

		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;

		interrupt-names = "macirq";

		mac-address = [00 55 7b b5 7d f7];

		clock-names = "axi",

			      "apb",

			      "mac_main",

			      "ptp_ref";

		clocks = <&pericfg CLK_PERI_GMAC>,

			 <&pericfg CLK_PERI_GMAC_PCLK>,

			 <&topckgen CLK_TOP_ETHER_125M_SEL>,

			 <&topckgen CLK_TOP_ETHER_50M_SEL>;

		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,

				  <&topckgen CLK_TOP_ETHER_50M_SEL>;

		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,

					 <&topckgen CLK_TOP_APLL1_D3>;

		power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;

		mediatek,pericfg = <&pericfg>;

		snps,axi-config = <&stmmac_axi_setup>;

		snps,mtl-rx-config = <&mtl_rx_setup>;

		snps,mtl-tx-config = <&mtl_tx_setup>;

		snps,txpbl = <1>;

		snps,rxpbl = <1>;

		clk_csr = <0>;

		status = "disabled";

	};



	mmc0: mmc@11230000 {

		compatible = "mediatek,mt2712-mmc";

		reg = <0 0x11230000 0 0x1000>;

arch/arm64/boot/dts/mediatek/mt7622.dtsi

+2 −5
Original line number Diff line number Diff line
@@ -244,7 +244,7 @@ 
		clock-names = "hif_sel";

	};



	cir: cir@10009000 {

	cir: ir-receiver@10009000 {

		compatible = "mediatek,mt7622-cir";

		reg = <0 0x10009000 0 0x1000>;

		interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
@@ -507,7 +507,6 @@ 
			 <&pericfg CLK_PERI_AUXADC_PD>;

		clock-names = "therm", "auxadc";

		resets = <&pericfg MT7622_PERI_THERM_SW_RST>;

		reset-names = "therm";

		mediatek,auxadc = <&auxadc>;

		mediatek,apmixedsys = <&apmixedsys>;

		nvmem-cells = <&thermal_calibration>;
@@ -901,9 +900,7 @@ 
	};



	eth: ethernet@1b100000 {

		compatible = "mediatek,mt7622-eth",

			     "mediatek,mt2701-eth",

			     "syscon";

		compatible = "mediatek,mt7622-eth";

		reg = <0 0x1b100000 0 0x20000>;

		interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,