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Commit 58908dc5 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'r8169-improve-eri-function-handling' 



Heiner Kallweit says:

====================
r8169: improve eri function handling

This series aims at improving and simplifying the eri functions.
No functional change intended.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents b4d081df 4e7e4621

drivers/net/ethernet/realtek/r8169.c

+122 −125
Original line number Diff line number Diff line
@@ -1065,7 +1065,7 @@ DECLARE_RTL_COND(rtl_eriar_cond) 
	return RTL_R32(tp, ERIAR) & ERIAR_FLAG;

}



static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,

static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,

			   u32 val, int type)

{

	BUG_ON((addr & 3) || (mask == 0));
@@ -1075,7 +1075,13 @@ static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask, 
	rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);

}



static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)

static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,

			  u32 val)

{

	_rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);

}



static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)

{

	RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
@@ -1083,13 +1089,30 @@ static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type) 
		RTL_R32(tp, ERIDR) : ~0;

}



static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)

{

	return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);

}



static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,

			 u32 m, int type)

			 u32 m)

{

	u32 val;



	val = rtl_eri_read(tp, addr, type);

	rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);

	val = rtl_eri_read(tp, addr);

	rtl_eri_write(tp, addr, mask, (val & ~m) | p);

}



static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 mask,

			     u32 p)

{

	rtl_w0w1_eri(tp, addr, mask, p, 0);

}



static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 mask,

			       u32 m)

{

	rtl_w0w1_eri(tp, addr, mask, 0, m);

}



static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
@@ -1101,7 +1124,7 @@ static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) 


static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)

{

	return rtl_eri_read(tp, reg, ERIAR_OOB);

	return _rtl_eri_read(tp, reg, ERIAR_OOB);

}



static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
@@ -1115,13 +1138,13 @@ static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, 
static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,

			      u32 data)

{

	rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,

	_rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,

		       data, ERIAR_OOB);

}



static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)

{

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);



	r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);

}
@@ -1257,6 +1280,12 @@ static bool r8168_check_dash(struct rtl8169_private *tp) 
	}

}



static void rtl_reset_packet_filter(struct rtl8169_private *tp)

{

	rtl_eri_clear_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));

	rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_0001, BIT(0));

}



struct exgmac_reg {

	u16 addr;

	u16 mask;
@@ -1267,7 +1296,7 @@ static void rtl_write_exgmac_batch(struct rtl8169_private *tp, 
				   const struct exgmac_reg *r, int len)

{

	while (len-- > 0) {

		rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);

		rtl_eri_write(tp, r->addr, r->mask, r->val);

		r++;

	}

}
@@ -1325,48 +1354,31 @@ static void rtl_link_chg_patch(struct rtl8169_private *tp) 
	if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||

	    tp->mac_version == RTL_GIGA_MAC_VER_38) {

		if (phydev->speed == SPEED_1000) {

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);

		} else if (phydev->speed == SPEED_100) {

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);

		} else {

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,

				      ERIAR_EXGMAC);

		}

		/* Reset packet filter */

		rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,

			     ERIAR_EXGMAC);

		rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,

			     ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);

		}

		rtl_reset_packet_filter(tp);

	} else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||

		   tp->mac_version == RTL_GIGA_MAC_VER_36) {

		if (phydev->speed == SPEED_1000) {

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);

		} else {

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);

		}

	} else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {

		if (phydev->speed == SPEED_10) {

			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);

			rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);

		} else {

			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,

				      ERIAR_EXGMAC);

			rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);

		}

	}

}
@@ -1407,19 +1419,11 @@ static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) 
	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:

		tmp = ARRAY_SIZE(cfg) - 1;

		if (wolopts & WAKE_MAGIC)

			rtl_w0w1_eri(tp,

				     0x0dc,

				     ERIAR_MASK_0100,

				     MagicPacket_v2,

				     0x0000,

				     ERIAR_EXGMAC);

			rtl_eri_set_bits(tp, 0x0dc, ERIAR_MASK_0100,

					 MagicPacket_v2);

		else

			rtl_w0w1_eri(tp,

				     0x0dc,

				     ERIAR_MASK_0100,

				     0x0000,

				     MagicPacket_v2,

				     ERIAR_EXGMAC);

			rtl_eri_clear_bits(tp, 0x0dc, ERIAR_MASK_0100,

					   MagicPacket_v2);

		break;

	default:

		tmp = ARRAY_SIZE(cfg);
@@ -2562,7 +2566,7 @@ static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) 


static void rtl8168_config_eee_mac(struct rtl8169_private *tp)

{

	rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);

	rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_1111, 0x0003);

}



static void rtl8168f_config_eee_phy(struct rtl8169_private *tp)
@@ -3959,7 +3963,7 @@ static void rtl8402_hw_phy_config(struct rtl8169_private *tp) 
	rtl_apply_firmware(tp);



	/* EEE setting */

	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);

	rtl_writephy(tp, 0x1f, 0x0004);

	rtl_writephy(tp, 0x10, 0x401f);

	rtl_writephy(tp, 0x19, 0x7030);
@@ -3982,10 +3986,10 @@ static void rtl8106e_hw_phy_config(struct rtl8169_private *tp) 


	rtl_apply_firmware(tp);



	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);

	rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));



	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);

}



static void rtl_hw_phy_config(struct net_device *dev)
@@ -4215,8 +4219,7 @@ static void r8168_pll_power_down(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_40:

	case RTL_GIGA_MAC_VER_41:

	case RTL_GIGA_MAC_VER_49:

		rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,

			     0xfc000000, ERIAR_EXGMAC);

		rtl_eri_clear_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);

		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);

		break;

	}
@@ -4244,8 +4247,7 @@ static void r8168_pll_power_up(struct rtl8169_private *tp) 
	case RTL_GIGA_MAC_VER_41:

	case RTL_GIGA_MAC_VER_49:

		RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);

		rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,

			     0x00000000, ERIAR_EXGMAC);

		rtl_eri_set_bits(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000);

		break;

	}
@@ -4996,14 +4998,14 @@ static void rtl_hw_start_8168e_2(struct rtl8169_private *tp) 
	if (tp->dev->mtu <= ETH_DATA_LEN)

		rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);

	rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));

	rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);



	RTL_W8(tp, MaxTxPacketSize, EarlySize);
@@ -5029,16 +5031,15 @@ static void rtl_hw_start_8168f(struct rtl8169_private *tp) 


	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);

	rtl_reset_packet_filter(tp);

	rtl_eri_set_bits(tp, 0x1b0, ERIAR_MASK_0001, BIT(4));

	rtl_eri_set_bits(tp, 0x1d0, ERIAR_MASK_0001, BIT(4));

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);



	RTL_W8(tp, MaxTxPacketSize, EarlySize);
@@ -5065,7 +5066,7 @@ static void rtl_hw_start_8168f_1(struct rtl8169_private *tp) 


	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));



	rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00);



	/* Adjust EEE LED frequency */

	RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
@@ -5085,37 +5086,36 @@ static void rtl_hw_start_8411(struct rtl8169_private *tp) 


	rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));



	rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);

	rtl_eri_set_bits(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00);

}



static void rtl_hw_start_8168g(struct rtl8169_private *tp)

{

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);



	rtl_set_def_aspm_entry_latency(tp);



	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);

	rtl_reset_packet_filter(tp);

	rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);



	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);

	RTL_W8(tp, MaxTxPacketSize, EarlySize);



	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);



	/* Adjust EEE LED frequency */

	RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);



	rtl8168_config_eee_mac(tp);



	rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);

	rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));



	rtl_pcie_state_l2l3_disable(tp);

}
@@ -5189,29 +5189,28 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 
	rtl_hw_aspm_clkreq_enable(tp, false);

	rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));



	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);



	rtl_set_def_aspm_entry_latency(tp);



	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);

	rtl_reset_packet_filter(tp);



	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);

	rtl_eri_set_bits(tp, 0xdc, ERIAR_MASK_1111, BIT(4));



	rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);

	rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f00);



	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);



	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);

	RTL_W8(tp, MaxTxPacketSize, EarlySize);



	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);



	/* Adjust EEE LED frequency */

	RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
@@ -5223,7 +5222,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp) 


	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);



	rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);

	rtl_eri_clear_bits(tp, 0x1b0, ERIAR_MASK_0011, BIT(12));



	rtl_pcie_state_l2l3_disable(tp);
@@ -5273,34 +5272,33 @@ static void rtl_hw_start_8168ep(struct rtl8169_private *tp) 
{

	rtl8168ep_stop_cmac(tp);



	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002);

	rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f);

	rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006);



	rtl_set_def_aspm_entry_latency(tp);



	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);

	rtl_reset_packet_filter(tp);



	rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);

	rtl_eri_set_bits(tp, 0xd4, ERIAR_MASK_1111, 0x1f80);



	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);



	RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);

	RTL_W8(tp, MaxTxPacketSize, EarlySize);



	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);



	/* Adjust EEE LED frequency */

	RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);



	rtl8168_config_eee_mac(tp);



	rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06);



	RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
@@ -5480,13 +5478,12 @@ static void rtl_hw_start_8402(struct rtl8169_private *tp) 


	rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);



	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);

	rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);

	rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002);

	rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006);

	rtl_reset_packet_filter(tp);

	rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);

	rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);

	rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00);



	rtl_pcie_state_l2l3_disable(tp);

}
@@ -6958,13 +6955,13 @@ static void rtl_read_mac_address(struct rtl8169_private *tp, 
	switch (tp->mac_version) {

	case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:

	case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:

		value = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);

		value = rtl_eri_read(tp, 0xe0);

		mac_addr[0] = (value >>  0) & 0xff;

		mac_addr[1] = (value >>  8) & 0xff;

		mac_addr[2] = (value >> 16) & 0xff;

		mac_addr[3] = (value >> 24) & 0xff;



		value = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);

		value = rtl_eri_read(tp, 0xe4);

		mac_addr[4] = (value >>  0) & 0xff;

		mac_addr[5] = (value >>  8) & 0xff;

		break;