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Commit 588dd859 authored by Murali Nalajala's avatar Murali Nalajala
Browse files

ARM: dts: qcom: add additional nodes for trusted VM 

Add additional nodes like more virtual CPUs, adjust pil segment offset
values for trusted VM and rearrange some of the nodes.

Change-Id: I290467a0ad2b62b52fc540a0ac6d4ec4feebe468
parent 7f92f703

qcom/trustedvm.dtsi

+89 −31
Original line number Diff line number Diff line
@@ -5,6 +5,16 @@ 
	#size-cells = <0x2>;

	interrupt-parent = <&vgic>;



	memory@28000000 {

		device_type = "memory";

		reg = <0x0 0x28800000 0x0 0x76f7000>; /* Temp S2 mapping */

	};



	qcom-mem-buf {

		compatible = "qcom,mem-buf";

		qcom,mem-buf-capabilities = "consumer";

	};



	chosen {

		bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8";

		linux,initrd-start = <0x2a900000>;
@@ -23,29 +33,62 @@ 
			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};



		CPU1: cpu@100 {

			compatible = "arm,armv8";

			reg = <0x0 0x100>;

			device_type = "cpu";

			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};



	vgic: interrupt-controller@17a00000 {

		compatible = "arm,gic-v3";

		interrupt-controller;

		#interrupt-cells = <0x3>;

		reg = <0x0 0x17a00000 0x0 0x10000>,     /* GICD */

		      <0x0 0x17a60000 0x0 0x100000>;    /* GICR * 8 */

		CPU2: cpu@200 {

			compatible = "arm,armv8";

			reg = <0x0 0x200>;

			device_type = "cpu";

			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

		CPU3: cpu@300 {

			compatible = "arm,armv8";

			reg = <0x0 0x300>;

			device_type = "cpu";

			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};



	qcom-mem-buf {

		compatible = "qcom,mem-buf";

		qcom,mem-buf-capabilities = "consumer";

		CPU4: cpu@400 {

			compatible = "arm,armv8";

			reg = <0x0 0x400>;

			device_type = "cpu";

			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};



	memory@28800000 {

		device_type = "memory";

		reg = <0x0 0x28800000 0x0 0x76f7000>; /* Temp S2 mapping */

		CPU5: cpu@500 {

			compatible = "arm,armv8";

			reg = <0x0 0x500>;

			device_type = "cpu";

			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};



		CPU6: cpu@600 {

			compatible = "arm,armv8";

			reg = <0x0 0x600>;

			device_type = "cpu";

			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};



		CPU7: cpu@700 {

			compatible = "arm,armv8";

			reg = <0x0 0x700>;

			device_type = "cpu";

			enable-method = "psci";

			cpu-idle-states = <0x2>;

		};

	};



	reserved_memory: reserved-memory {
@@ -125,13 +168,14 @@ 
			#address-cells = <0x2>;

			#size-cells = <0x0>;

			base-address = <0x0 0xD0800000>;

			size-min = <0x0 0x8000000>;    /* 128 MB */

			size-min = <0x0 0x7800000>;    /* 120 MB */

		};



		segments {

			/* offset and size */

			kernel = <0x0 0x8000 0x0 0x2000000>;  /* 32 MB */

			dt = <0x0 0x7000000 0x0 0x4000>;      /* 16 KB */

			kernel = <0x0 0x80000 0x0 0x1f80000>;    /* 31MB */

			dt = <0x0 0x2000000 0x0 0x100000>;       /* 1MB */

			ramdisk = <0x0 0x2100000 0x0 0x800000>; /* 8MB */

		};



		vcpus {
@@ -149,14 +193,6 @@ 
		};

	};



	arch_timer: timer {

		compatible = "arm,armv8-timer";

		always-on;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

	};

	soc: soc { };

};
@@ -181,6 +217,28 @@ 
		qcom,ee = <0>;

	};



	psci {

		compatible = "arm,psci-1.0";

		method = "smc";

	};



	vgic: interrupt-controller@17a00000 {

		compatible = "arm,gic-v3";

		interrupt-controller;

		#interrupt-cells = <0x3>;

		reg = <0x17a00000 0x10000>,     /* GICD */

		      <0x17a60000 0x100000>;    /* GICR * 8 */

	};



	arch_timer: timer {

		compatible = "arm,armv8-timer";

		always-on;

		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

	};



	/*

	 * QUPv3 Instances

	 * North 4 : SE 4