Merge branch 'drivers-for-4.20' into drivers-for-4.20-final

- reg:

	Usage: required

	Value Type: <prop-encoded-array>

	Definition: Start address and the the size of the register region.

	Definition: The first element specifies the llcc base start address and

		    the size of the register region. The second element specifies

		    the llcc broadcast base address and size of the register region.

- reg-names:

        Usage: required

        Value Type: <stringlist>

        Definition: Register region names. Must be "llcc_base", "llcc_broadcast_base".

- interrupts:

	Usage: required

	Definition: The interrupt is associated with the llcc edac device.

			It's used for llcc cache single and double bit error detection

			and reporting.

Example:

	cache-controller@1100000 {

		compatible = "qcom,sdm845-llcc";

		reg = <0x1100000 0x250000>;

		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;

		reg-names = "llcc_base", "llcc_broadcast_base";

		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;

	};

Required properties:

- compatible: must contain one of the following:

 * "qcom,scm-apq8064" for APQ8064 platforms

 * "qcom,scm-msm8660" for MSM8660 platforms

 * "qcom,scm-msm8690" for MSM8690 platforms

 * "qcom,scm-msm8996" for MSM8996 platforms

 * "qcom,scm-ipq4019" for IPQ4019 platforms

 * "qcom,scm" for later processors (MSM8916, APQ8084, MSM8974, etc)

- clocks: One to three clocks may be required based on compatible.

 * No clock required for "qcom,scm-msm8996", "qcom,scm-ipq4019"

 * Only core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660", and "qcom,scm-msm8960"

 * Core, iface, and bus clocks required for "qcom,scm"

 * "qcom,scm-apq8064"

 * "qcom,scm-apq8084"

 * "qcom,scm-msm8660"

 * "qcom,scm-msm8916"

 * "qcom,scm-msm8960"

 * "qcom,scm-msm8974"

 * "qcom,scm-msm8996"

 * "qcom,scm-msm8998"

 * "qcom,scm-ipq4019"

 * "qcom,scm-sdm845"

 and:

 * "qcom,scm"

- clocks: Specifies clocks needed by the SCM interface, if any:

 * core clock required for "qcom,scm-apq8064", "qcom,scm-msm8660" and

   "qcom,scm-msm8960"

 * core, iface and bus clocks required for "qcom,scm-apq8084",

   "qcom,scm-msm8916" and "qcom,scm-msm8974"

- clock-names: Must contain "core" for the core clock, "iface" for the interface

  clock and "bus" for the bus clock per the requirements of the compatible.

- qcom,dload-mode: phandle to the TCSR hardware block and offset of the

	firmware {

		scm {

			compatible = "qcom,scm";

			clocks = <&gcc GCC_CRYPTO_CLK> , <&gcc GCC_CRYPTO_AXI_CLK>, <&gcc GCC_CRYPTO_AHB_CLK>;

			compatible = "qcom,msm8916", "qcom,scm";

			clocks = <&gcc GCC_CRYPTO_CLK> ,

				 <&gcc GCC_CRYPTO_AXI_CLK>,

				 <&gcc GCC_CRYPTO_AHB_CLK>;

			clock-names = "core", "bus", "iface";

		};

	};

S:	Maintained

F:	drivers/edac/ti_edac.c

EDAC-QCOM

M:	Channagoud Kadabi <ckadabi@codeaurora.org>

M:	Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>

L:	linux-arm-msm@vger.kernel.org

L:	linux-edac@vger.kernel.org

S:	Maintained

F:	drivers/edac/qcom_edac.c

EDIROL UA-101/UA-1000 DRIVER

M:	Clemens Ladisch <clemens@ladisch.de>

L:	alsa-devel@alsa-project.org (moderated for non-subscribers)

	  Support for error detection and correction on the

          TI SoCs.

config EDAC_QCOM

	tristate "QCOM EDAC Controller"

	depends on ARCH_QCOM && QCOM_LLCC

	help

	  Support for error detection and correction on the

	  Qualcomm Technologies, Inc. SoCs.

	  This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).

	  As of now, it supports error reporting for Last Level Cache Controller (LLCC)

	  of Tag RAM and Data RAM.

	  For debugging issues having to do with stability and overall system

	  health, you should probably say 'Y' here.

endif # EDAC

obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o

obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o

obj-$(CONFIG_EDAC_TI)			+= ti_edac.o

obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o