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Commit 57527f8d authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville
Browse files

ath9k_hw: Program filter coefficients correctly 



2484 Mhz (Japan) usage requires filter coefficients to
be programmed in the CCK TX FIR registers. This is required
for AR9331, AR9485 and AR9462. Fix this and also remove
a few useless macros and a duplicate variable.

Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent f3684343

drivers/net/wireless/ath/ath9k/ar9003_hw.c

+13 −9
Original line number Diff line number Diff line
@@ -35,12 +35,6 @@ 
 */

static void ar9003_hw_init_mode_regs(struct ath_hw *ah)

{

#define AR9462_BB_CTX_COEFJ(x)	\

		ar9462_##x##_baseband_core_txfir_coeff_japan_2484



#define AR9462_BBC_TXIFR_COEFFJ \

		ar9462_2p0_baseband_core_txfir_coeff_japan_2484



	if (AR_SREV_9330_11(ah)) {

		/* mac */

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
@@ -70,6 +64,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
		INIT_INI_ARRAY(&ah->iniModesTxGain,

				ar9331_modes_lowest_ob_db_tx_gain_1p1);



		/* Japan 2484 Mhz CCK */

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

			       ar9331_1p1_baseband_core_txfir_coeff_japan_2484);



		/* additional clock settings */

		if (ah->is_clk_25mhz)

			INIT_INI_ARRAY(&ah->iniAdditional,
@@ -106,6 +104,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
		INIT_INI_ARRAY(&ah->iniModesTxGain,

				ar9331_modes_lowest_ob_db_tx_gain_1p2);



		/* Japan 2484 Mhz CCK */

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

			       ar9331_1p2_baseband_core_txfir_coeff_japan_2484);



		/* additional clock settings */

		if (ah->is_clk_25mhz)

			INIT_INI_ARRAY(&ah->iniAdditional,
@@ -180,6 +182,10 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
		INIT_INI_ARRAY(&ah->iniModesTxGain,

				ar9485_modes_lowest_ob_db_tx_gain_1_1);



		/* Japan 2484 Mhz CCK */

		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

			       ar9485_1_1_baseband_core_txfir_coeff_japan_2484);



		/* Load PCIE SERDES settings from INI */



		/* Awake Setting */
@@ -229,9 +235,7 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) 
				ar9462_modes_fast_clock_2p0);



		INIT_INI_ARRAY(&ah->iniCckfirJapan2484,

				AR9462_BB_CTX_COEFJ(2p0));



		INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ);

			       ar9462_2p0_baseband_core_txfir_coeff_japan_2484);

	} else if (AR_SREV_9550(ah)) {

		/* mac */

		INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],

drivers/net/wireless/ath/ath9k/ar9003_phy.c

+1 −1
Original line number Diff line number Diff line
@@ -784,7 +784,7 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, 
	REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);



	if (chan->channel == 2484)

		ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);

		ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);



	if (AR_SREV_9462(ah) || AR_SREV_9565(ah))

		REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,

drivers/net/wireless/ath/ath9k/ar9485_initvals.h

+2 −0
Original line number Diff line number Diff line
@@ -1060,4 +1060,6 @@ static const u32 ar9485_1_1_mac_core[][2] = { 
	{0x000083d0, 0x000301ff},

};



#define ar9485_1_1_baseband_core_txfir_coeff_japan_2484 ar9462_2p0_baseband_core_txfir_coeff_japan_2484



#endif /* INITVALS_9485_H */

drivers/net/wireless/ath/ath9k/hw.h

+0 −1
Original line number Diff line number Diff line
@@ -875,7 +875,6 @@ struct ath_hw { 
	struct ar5416IniArray iniModesTxGain;

	struct ar5416IniArray iniCckfirNormal;

	struct ar5416IniArray iniCckfirJapan2484;

	struct ar5416IniArray ini_japan2484;

	struct ar5416IniArray iniModes_9271_ANI_reg;

	struct ar5416IniArray ini_radio_post_sys2ant;