Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 57113c01 authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nouveau/therm: convert to new-style nvkm_subdev 



Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent e2ca4e7d

drivers/gpu/drm/nouveau/include/nvif/device.h

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ u64 nvif_device_time(struct nvif_device *); 
#define nvxx_gpio(a) nvxx_device(a)->gpio

#define nvxx_clk(a) nvxx_device(a)->clk

#define nvxx_i2c(a) nvxx_device(a)->i2c

#define nvxx_therm(a) nvkm_therm(nvxx_device(a))

#define nvxx_therm(a) nvxx_device(a)->therm



#include <core/device.h>

#include <engine/fifo.h>

drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h

+62 −42
Original line number Diff line number Diff line
@@ -2,6 +2,28 @@ 
#define __NVKM_THERM_H__

#include <core/subdev.h>



#include <subdev/bios.h>

#include <subdev/bios/therm.h>

#include <subdev/timer.h>



enum nvkm_therm_thrs_direction {

	NVKM_THERM_THRS_FALLING = 0,

	NVKM_THERM_THRS_RISING = 1

};



enum nvkm_therm_thrs_state {

	NVKM_THERM_THRS_LOWER = 0,

	NVKM_THERM_THRS_HIGHER = 1

};



enum nvkm_therm_thrs {

	NVKM_THERM_THRS_FANBOOST = 0,

	NVKM_THERM_THRS_DOWNCLOCK = 1,

	NVKM_THERM_THRS_CRITICAL = 2,

	NVKM_THERM_THRS_SHUTDOWN = 3,

	NVKM_THERM_THRS_NR

};



enum nvkm_therm_fan_mode {

	NVKM_THERM_CTRL_NONE = 0,

	NVKM_THERM_CTRL_MANUAL = 1,
@@ -24,56 +46,54 @@ enum nvkm_therm_attr_type { 
};



struct nvkm_therm {

	const struct nvkm_therm_func *func;

	struct nvkm_subdev subdev;



	int (*pwm_ctrl)(struct nvkm_therm *, int line, bool);

	int (*pwm_get)(struct nvkm_therm *, int line, u32 *, u32 *);

	int (*pwm_set)(struct nvkm_therm *, int line, u32, u32);

	int (*pwm_clock)(struct nvkm_therm *, int line);

	/* automatic thermal management */

	struct nvkm_alarm alarm;

	spinlock_t lock;

	struct nvbios_therm_trip_point *last_trip;

	int mode;

	int cstate;

	int suspend;



	/* bios */

	struct nvbios_therm_sensor bios_sensor;



	/* fan priv */

	struct nvkm_fan *fan;



	/* alarms priv */

	struct {

		spinlock_t alarm_program_lock;

		struct nvkm_alarm therm_poll_alarm;

		enum nvkm_therm_thrs_state alarm_state[NVKM_THERM_THRS_NR];

	} sensor;



	/* what should be done if the card overheats */

	struct {

		void (*downclock)(struct nvkm_therm *, bool active);

		void (*pause)(struct nvkm_therm *, bool active);

	} emergency;



	/* ic */

	struct i2c_client *ic;



	int (*fan_get)(struct nvkm_therm *);

	int (*fan_set)(struct nvkm_therm *, int);

	int (*fan_sense)(struct nvkm_therm *);



	int (*temp_get)(struct nvkm_therm *);



	int (*attr_get)(struct nvkm_therm *, enum nvkm_therm_attr_type);

	int (*attr_set)(struct nvkm_therm *, enum nvkm_therm_attr_type, int);

};



static inline struct nvkm_therm *

nvkm_therm(void *obj)

{

	return (void *)nvkm_subdev(obj, NVDEV_SUBDEV_THERM);

}



#define nvkm_therm_create(p,e,o,d)                                          \

	nvkm_therm_create_((p), (e), (o), sizeof(**d), (void **)d)

#define nvkm_therm_destroy(p) ({                                            \

	struct nvkm_therm *_therm = (p);                                     \

        _nvkm_therm_dtor(nv_object(_therm));                                 \

})

#define nvkm_therm_init(p) ({                                               \

	struct nvkm_therm *_therm = (p);                                     \

        _nvkm_therm_init(nv_object(_therm));                                 \

})

#define nvkm_therm_fini(p,s) ({                                             \

	struct nvkm_therm *_therm = (p);                                     \

        _nvkm_therm_init(nv_object(_therm), (s));                            \

})



int  nvkm_therm_create_(struct nvkm_object *, struct nvkm_object *,

			   struct nvkm_oclass *, int, void **);

void _nvkm_therm_dtor(struct nvkm_object *);

int  _nvkm_therm_init(struct nvkm_object *);

int  _nvkm_therm_fini(struct nvkm_object *, bool);



int nvkm_therm_temp_get(struct nvkm_therm *);

int nvkm_therm_fan_sense(struct nvkm_therm *);

int nvkm_therm_cstate(struct nvkm_therm *, int, int);



extern struct nvkm_oclass nv40_therm_oclass;

extern struct nvkm_oclass nv50_therm_oclass;

extern struct nvkm_oclass g84_therm_oclass;

extern struct nvkm_oclass gt215_therm_oclass;

extern struct nvkm_oclass gf110_therm_oclass;

extern struct nvkm_oclass gm107_therm_oclass;

int nv40_therm_new(struct nvkm_device *, int, struct nvkm_therm **);

int nv50_therm_new(struct nvkm_device *, int, struct nvkm_therm **);

int g84_therm_new(struct nvkm_device *, int, struct nvkm_therm **);

int gt215_therm_new(struct nvkm_device *, int, struct nvkm_therm **);

int gf119_therm_new(struct nvkm_device *, int, struct nvkm_therm **);

int gm107_therm_new(struct nvkm_device *, int, struct nvkm_therm **);

#endif

drivers/gpu/drm/nouveau/nouveau_hwmon.c

+5 −5
Original line number Diff line number Diff line
@@ -41,7 +41,7 @@ nouveau_hwmon_show_temp(struct device *d, struct device_attribute *a, char *buf) 
	struct drm_device *dev = dev_get_drvdata(d);

	struct nouveau_drm *drm = nouveau_drm(dev);

	struct nvkm_therm *therm = nvxx_therm(&drm->device);

	int temp = therm->temp_get(therm);

	int temp = nvkm_therm_temp_get(therm);



	if (temp < 0)

		return temp;
@@ -348,7 +348,7 @@ nouveau_hwmon_show_fan1_input(struct device *d, struct device_attribute *attr, 
	struct nouveau_drm *drm = nouveau_drm(dev);

	struct nvkm_therm *therm = nvxx_therm(&drm->device);



	return snprintf(buf, PAGE_SIZE, "%d\n", therm->fan_sense(therm));

	return snprintf(buf, PAGE_SIZE, "%d\n", nvkm_therm_fan_sense(therm));

}

static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, nouveau_hwmon_show_fan1_input,

			  NULL, 0);
@@ -571,7 +571,7 @@ nouveau_hwmon_init(struct drm_device *dev) 
		return -ENOMEM;

	hwmon->dev = dev;



	if (!therm || !therm->temp_get || !therm->attr_get || !therm->attr_set)

	if (!therm || !therm->attr_get || !therm->attr_set)

		return -ENODEV;



	hwmon_dev = hwmon_device_register(&dev->pdev->dev);
@@ -588,7 +588,7 @@ nouveau_hwmon_init(struct drm_device *dev) 
		goto error;



	/* if the card has a working thermal sensor */

	if (therm->temp_get(therm) >= 0) {

	if (nvkm_therm_temp_get(therm) >= 0) {

		ret = sysfs_create_group(&hwmon_dev->kobj, &hwmon_temp_attrgroup);

		if (ret)

			goto error;
@@ -606,7 +606,7 @@ nouveau_hwmon_init(struct drm_device *dev) 
	}



	/* if the card can read the fan rpm */

	if (therm->fan_sense(therm) >= 0) {

	if (nvkm_therm_fan_sense(therm) >= 0) {

		ret = sysfs_create_group(&hwmon_dev->kobj,

					 &hwmon_fan_rpm_attrgroup);

		if (ret)

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

+47 −47
Original line number Diff line number Diff line
@@ -463,7 +463,7 @@ nv40_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv40_mc_new,

	.mmu = nv04_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -488,7 +488,7 @@ nv41_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv40_mc_new,

	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -513,7 +513,7 @@ nv42_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv40_mc_new,

	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -538,7 +538,7 @@ nv43_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv40_mc_new,

	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -563,7 +563,7 @@ nv44_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv44_mc_new,

	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -588,7 +588,7 @@ nv45_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv40_mc_new,

	.mmu = nv04_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -613,7 +613,7 @@ nv46_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv44_mc_new,

	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -638,7 +638,7 @@ nv47_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv40_mc_new,

	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -663,7 +663,7 @@ nv49_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv40_mc_new,

	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -688,7 +688,7 @@ nv4a_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv44_mc_new,

	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -713,7 +713,7 @@ nv4b_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv40_mc_new,

	.mmu = nv41_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -738,7 +738,7 @@ nv4c_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv4c_mc_new,

	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -763,7 +763,7 @@ nv4e_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv4c_mc_new,

	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -791,7 +791,7 @@ nv50_chipset = { 
	.mc = nv50_mc_new,

	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = nv50_therm_new,

	.therm = nv50_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv50_disp_new,
@@ -816,7 +816,7 @@ nv63_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv4c_mc_new,

	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -841,7 +841,7 @@ nv67_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv4c_mc_new,

	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -866,7 +866,7 @@ nv68_chipset = { 
	.imem = nv40_instmem_new,

	.mc = nv4c_mc_new,

	.mmu = nv44_mmu_new,

//	.therm = nv40_therm_new,

	.therm = nv40_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = nv04_disp_new,
@@ -894,7 +894,7 @@ nv84_chipset = { 
	.mc = nv50_mc_new,

	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.bsp = g84_bsp_new,
@@ -925,7 +925,7 @@ nv86_chipset = { 
	.mc = nv50_mc_new,

	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.bsp = g84_bsp_new,
@@ -956,7 +956,7 @@ nv92_chipset = { 
	.mc = nv50_mc_new,

	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.bsp = g84_bsp_new,
@@ -987,7 +987,7 @@ nv94_chipset = { 
	.mc = g94_mc_new,

	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.bsp = g84_bsp_new,
@@ -1010,7 +1010,7 @@ nv96_chipset = { 
	.i2c = g94_i2c_new,

	.fuse = nv50_fuse_new,

	.clk = g84_clk_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

	.mxm = nv50_mxm_new,

	.devinit = g84_devinit_new,

	.mc = g94_mc_new,
@@ -1041,7 +1041,7 @@ nv98_chipset = { 
	.i2c = g94_i2c_new,

	.fuse = nv50_fuse_new,

	.clk = g84_clk_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

	.mxm = nv50_mxm_new,

	.devinit = g98_devinit_new,

	.mc = g98_mc_new,
@@ -1080,7 +1080,7 @@ nva0_chipset = { 
	.mc = g98_mc_new,

	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.bsp = g84_bsp_new,
@@ -1112,7 +1112,7 @@ nva3_chipset = { 
	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gt215_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gt215_ce_new,
@@ -1145,7 +1145,7 @@ nva5_chipset = { 
	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gt215_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gt215_ce_new,
@@ -1177,7 +1177,7 @@ nva8_chipset = { 
	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gt215_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gt215_ce_new,
@@ -1208,7 +1208,7 @@ nvaa_chipset = { 
	.mc = g98_mc_new,

	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = g94_disp_new,
@@ -1239,7 +1239,7 @@ nvac_chipset = { 
	.mc = g98_mc_new,

	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = g84_therm_new,

	.therm = g84_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.disp = g94_disp_new,
@@ -1271,7 +1271,7 @@ nvaf_chipset = { 
	.mmu = nv50_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gt215_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gt215_ce_new,
@@ -1305,7 +1305,7 @@ nvc0_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf100_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gf100_ce0_new,
@@ -1340,7 +1340,7 @@ nvc1_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf100_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gf100_ce0_new,
@@ -1374,7 +1374,7 @@ nvc3_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf100_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gf100_ce0_new,
@@ -1408,7 +1408,7 @@ nvc4_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf100_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gf100_ce0_new,
@@ -1443,7 +1443,7 @@ nvc8_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf100_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gf100_ce0_new,
@@ -1478,7 +1478,7 @@ nvce_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf100_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gf100_ce0_new,
@@ -1513,7 +1513,7 @@ nvcf_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf100_pmu_new,

//	.therm = gt215_therm_new,

	.therm = gt215_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gf100_ce0_new,
@@ -1546,7 +1546,7 @@ nvd7_chipset = { 
	.mc = gf106_mc_new,

	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.ce[0] = gf100_ce0_new,

//	.disp = gf119_disp_new,
@@ -1579,7 +1579,7 @@ nvd9_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf119_pmu_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gf100_ce0_new,
@@ -1613,7 +1613,7 @@ nve4_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gk104_pmu_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gk104_ce0_new,
@@ -1649,7 +1649,7 @@ nve6_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gk104_pmu_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gk104_ce0_new,
@@ -1685,7 +1685,7 @@ nve7_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gf119_pmu_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gk104_ce0_new,
@@ -1745,7 +1745,7 @@ nvf0_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gk110_pmu_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gk104_ce0_new,
@@ -1781,7 +1781,7 @@ nvf1_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gk110_pmu_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gk104_ce0_new,
@@ -1817,7 +1817,7 @@ nv106_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gk208_pmu_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gk104_ce0_new,
@@ -1852,7 +1852,7 @@ nv108_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gk208_pmu_new,

//	.therm = gf110_therm_new,

	.therm = gf119_therm_new,

//	.timer = nv04_timer_new,

//	.volt = nv40_volt_new,

//	.ce[0] = gk104_ce0_new,
@@ -1887,7 +1887,7 @@ nv117_chipset = { 
	.mmu = gf100_mmu_new,

	.mxm = nv50_mxm_new,

	.pmu = gm107_pmu_new,

//	.therm = gm107_therm_new,

	.therm = gm107_therm_new,

//	.timer = gk20a_timer_new,

//	.ce[0] = gk104_ce0_new,

//	.ce[2] = gk104_ce2_new,

drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c

+0 −9
Original line number Diff line number Diff line
@@ -28,7 +28,6 @@ gf100_identify(struct nvkm_device *device) 
{

	switch (device->chipset) {

	case 0xc0:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -44,7 +43,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc4:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -60,7 +58,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc3:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -75,7 +72,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xce:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -91,7 +87,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xcf:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -106,7 +101,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xc1:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -121,7 +115,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf108_pm_oclass;

		break;

	case 0xc8:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gt215_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf100_dmaeng_oclass;
@@ -137,7 +130,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf100_pm_oclass;

		break;

	case 0xd9:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_SUBDEV_VOLT   ] = &nv40_volt_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;
@@ -152,7 +144,6 @@ gf100_identify(struct nvkm_device *device) 
		device->oclass[NVDEV_ENGINE_PM     ] = gf117_pm_oclass;

		break;

	case 0xd7:

		device->oclass[NVDEV_SUBDEV_THERM  ] = &gf110_therm_oclass;

		device->oclass[NVDEV_SUBDEV_TIMER  ] = &nv04_timer_oclass;

		device->oclass[NVDEV_ENGINE_DMAOBJ ] =  gf110_dmaeng_oclass;

		device->oclass[NVDEV_ENGINE_FIFO   ] =  gf100_fifo_oclass;