Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 56f3c141 authored by Christophe Leroy's avatar Christophe Leroy Committed by Michael Ellerman
Browse files

powerpc/mm: properly set PAGE_KERNEL flags in ioremap() 



Set PAGE_KERNEL directly in the caller and do not rely on a
hack adding PAGE_KERNEL flags when _PAGE_PRESENT is not set.

As already done for PPC64, use pgprot_cache() helpers instead of
_PAGE_XXX flags in PPC32 ioremap() derived functions.

Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
parent aa91796e

arch/powerpc/include/asm/nohash/pgtable.h

+2 −0
Original line number Diff line number Diff line
@@ -197,6 +197,8 @@ extern int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long addre 
#if _PAGE_WRITETHRU != 0

#define pgprot_cached_wthru(prot) (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \

				            _PAGE_COHERENT | _PAGE_WRITETHRU))

#else

#define pgprot_cached_wthru(prot)	pgprot_noncached(prot)

#endif



#define pgprot_cached_noncoherent(prot) \

arch/powerpc/kernel/isa-bridge.c

+3 −3
Original line number Diff line number Diff line
@@ -110,14 +110,14 @@ static void pci_process_ISA_OF_ranges(struct device_node *isa_node, 
		size = 0x10000;



	__ioremap_at(phb_io_base_phys, (void *)ISA_IO_BASE,

		     size, pgprot_val(pgprot_noncached(__pgprot(0))));

		     size, pgprot_val(pgprot_noncached(PAGE_KERNEL)));

	return;



inval_range:

	printk(KERN_ERR "no ISA IO ranges or unexpected isa range, "

	       "mapping 64k\n");

	__ioremap_at(phb_io_base_phys, (void *)ISA_IO_BASE,

		     0x10000, pgprot_val(pgprot_noncached(__pgprot(0))));

		     0x10000, pgprot_val(pgprot_noncached(PAGE_KERNEL)));

}
@@ -253,7 +253,7 @@ void __init isa_bridge_init_non_pci(struct device_node *np) 
	 */

	isa_io_base = ISA_IO_BASE;

	__ioremap_at(pbase, (void *)ISA_IO_BASE,

		     size, pgprot_val(pgprot_noncached(__pgprot(0))));

		     size, pgprot_val(pgprot_noncached(PAGE_KERNEL)));



	pr_debug("ISA: Non-PCI bridge is %pOF\n", np);

}

arch/powerpc/kernel/pci_64.c

+1 −1
Original line number Diff line number Diff line
@@ -159,7 +159,7 @@ static int pcibios_map_phb_io_space(struct pci_controller *hose) 


	/* Establish the mapping */

	if (__ioremap_at(phys_page, area->addr, size_page,

			 pgprot_val(pgprot_noncached(__pgprot(0)))) == NULL)

			 pgprot_val(pgprot_noncached(PAGE_KERNEL))) == NULL)

		return -ENOMEM;



	/* Fixup hose IO resource */

arch/powerpc/mm/pgtable_32.c

+12 −16
Original line number Diff line number Diff line
@@ -76,32 +76,36 @@ pgtable_t pte_alloc_one(struct mm_struct *mm, unsigned long address) 
void __iomem *

ioremap(phys_addr_t addr, unsigned long size)

{

	return __ioremap_caller(addr, size, _PAGE_NO_CACHE | _PAGE_GUARDED,

				__builtin_return_address(0));

	unsigned long flags = pgprot_val(pgprot_noncached(PAGE_KERNEL));



	return __ioremap_caller(addr, size, flags, __builtin_return_address(0));

}

EXPORT_SYMBOL(ioremap);



void __iomem *

ioremap_wc(phys_addr_t addr, unsigned long size)

{

	return __ioremap_caller(addr, size, _PAGE_NO_CACHE,

				__builtin_return_address(0));

	unsigned long flags = pgprot_val(pgprot_noncached_wc(PAGE_KERNEL));



	return __ioremap_caller(addr, size, flags, __builtin_return_address(0));

}

EXPORT_SYMBOL(ioremap_wc);



void __iomem *

ioremap_wt(phys_addr_t addr, unsigned long size)

{

	return __ioremap_caller(addr, size, _PAGE_WRITETHRU,

				__builtin_return_address(0));

	unsigned long flags = pgprot_val(pgprot_cached_wthru(PAGE_KERNEL));



	return __ioremap_caller(addr, size, flags, __builtin_return_address(0));

}

EXPORT_SYMBOL(ioremap_wt);



void __iomem *

ioremap_coherent(phys_addr_t addr, unsigned long size)

{

	return __ioremap_caller(addr, size, _PAGE_COHERENT,

				__builtin_return_address(0));

	unsigned long flags = pgprot_val(pgprot_cached(PAGE_KERNEL));



	return __ioremap_caller(addr, size, flags, __builtin_return_address(0));

}

EXPORT_SYMBOL(ioremap_coherent);
@@ -134,14 +138,6 @@ __ioremap_caller(phys_addr_t addr, unsigned long size, unsigned long flags, 
	phys_addr_t p;

	int err;



	/* Make sure we have the base flags */

	if ((flags & _PAGE_PRESENT) == 0)

		flags |= pgprot_val(PAGE_KERNEL);



	/* Non-cacheable page cannot be coherent */

	if (flags & _PAGE_NO_CACHE)

		flags &= ~_PAGE_COHERENT;



	/*

	 * Choose an address to map it to.

	 * Once the vmalloc system is running, we use it.

arch/powerpc/mm/pgtable_64.c

+3 −7
Original line number Diff line number Diff line
@@ -118,10 +118,6 @@ void __iomem * __ioremap_at(phys_addr_t pa, void *ea, unsigned long size, 
{

	unsigned long i;



	/* Make sure we have the base flags */

	if ((flags & _PAGE_PRESENT) == 0)

		flags |= pgprot_val(PAGE_KERNEL);



	/* We don't support the 4K PFN hack with ioremap */

	if (flags & H_PAGE_4K_PFN)

		return NULL;
@@ -204,7 +200,7 @@ void __iomem * __ioremap(phys_addr_t addr, unsigned long size, 


void __iomem * ioremap(phys_addr_t addr, unsigned long size)

{

	unsigned long flags = pgprot_val(pgprot_noncached(__pgprot(0)));

	unsigned long flags = pgprot_val(pgprot_noncached(PAGE_KERNEL));

	void *caller = __builtin_return_address(0);



	if (ppc_md.ioremap)
@@ -214,7 +210,7 @@ void __iomem * ioremap(phys_addr_t addr, unsigned long size) 


void __iomem * ioremap_wc(phys_addr_t addr, unsigned long size)

{

	unsigned long flags = pgprot_val(pgprot_noncached_wc(__pgprot(0)));

	unsigned long flags = pgprot_val(pgprot_noncached_wc(PAGE_KERNEL));

	void *caller = __builtin_return_address(0);



	if (ppc_md.ioremap)
@@ -224,7 +220,7 @@ void __iomem * ioremap_wc(phys_addr_t addr, unsigned long size) 


void __iomem *ioremap_coherent(phys_addr_t addr, unsigned long size)

{

	unsigned long flags = pgprot_val(pgprot_cached(__pgprot(0)));

	unsigned long flags = pgprot_val(pgprot_cached(PAGE_KERNEL));

	void *caller = __builtin_return_address(0);



	if (ppc_md.ioremap)