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Commit 56e04191 authored by Rajkumar Subbiah's avatar Rajkumar Subbiah
Browse files

disp: msm: dsi: add widebus support for DSI 



From Lahaina onwards, for compressed DSI output, widebus should be enabled.
In widebus mode, 6 bytes of data are transmitted per pclk.
For uncompressed output, widebus must be disabled to transmit 3 bytes
of uncompressed data per pclk.

Change-Id: I7fc0bdb2e1678152d57b4cbb8295063a2ba8ae73
Signed-off-by: default avatarRajkumar Subbiah <rsubbia@codeaurora.org>
parent c0d4857a

msm/dsi/dsi_catalog.c

+4 −0
Original line number Diff line number Diff line
@@ -163,7 +163,11 @@ int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, 
	case DSI_CTRL_VERSION_2_2:

	case DSI_CTRL_VERSION_2_3:

	case DSI_CTRL_VERSION_2_4:

		ctrl->phy_isolation_enabled = phy_isolation_enabled;

		dsi_catalog_cmn_init(ctrl, version);

		break;

	case DSI_CTRL_VERSION_2_5:

		ctrl->widebus_support = true;

		ctrl->phy_isolation_enabled = phy_isolation_enabled;

		dsi_catalog_cmn_init(ctrl, version);

		break;

msm/dsi/dsi_catalog.h

+1 −1
Original line number Diff line number Diff line
@@ -170,7 +170,7 @@ void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on); 


void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,

				     struct dsi_mode_info *mode,

				     u32 h_stride,

				     struct dsi_host_common_cfg *cfg,

				     u32 vc_id,

				     struct dsi_rect *roi);

void dsi_ctrl_hw_cmn_phy_sw_reset(struct dsi_ctrl_hw *ctrl);

msm/dsi/dsi_ctrl.c

+3 −3
Original line number Diff line number Diff line
@@ -2255,7 +2255,7 @@ int dsi_ctrl_timing_setup(struct dsi_ctrl *dsi_ctrl) 


		dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,

				&dsi_ctrl->host_config.video_timing,

				dsi_ctrl->host_config.video_timing.h_active * 3,

				&dsi_ctrl->host_config.common_config,

				0x0,

				&dsi_ctrl->roi);

		dsi_ctrl->hw.ops.cmd_engine_en(&dsi_ctrl->hw, true);
@@ -2714,7 +2714,7 @@ int dsi_ctrl_host_timing_update(struct dsi_ctrl *dsi_ctrl) 
		if (dsi_ctrl->hw.ops.setup_cmd_stream)

			dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,

				&dsi_ctrl->host_config.video_timing,

				dsi_ctrl->host_config.video_timing.h_active * 3,

				&dsi_ctrl->host_config.common_config,

				0x0, NULL);

	} else {

		DSI_CTRL_ERR(dsi_ctrl, "invalid panel mode for resolution switch\n");
@@ -2802,7 +2802,7 @@ int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl, bool is_splash_enabled) 


			dsi_ctrl->hw.ops.setup_cmd_stream(&dsi_ctrl->hw,

				&dsi_ctrl->host_config.video_timing,

				dsi_ctrl->host_config.video_timing.h_active * 3,

				&dsi_ctrl->host_config.common_config,

				0x0,

				NULL);

		} else {

msm/dsi/dsi_ctrl_hw.h

+5 −2
Original line number Diff line number Diff line
@@ -432,14 +432,15 @@ struct dsi_ctrl_hw_ops { 
	 * setup_cmd_stream() - set up parameters for command pixel streams

	 * @ctrl:              Pointer to controller host hardware.

	 * @mode:              Pointer to mode information.

	 * @h_stride:          Horizontal stride in bytes.

	 * @cfg:               DSI host configuration that is common to both

	 *                     video and command modes.

	 * @vc_id:             stream_id.

	 *

	 * Setup parameters for command mode pixel stream size.

	 */

	void (*setup_cmd_stream)(struct dsi_ctrl_hw *ctrl,

				 struct dsi_mode_info *mode,

				 u32 h_stride,

				 struct dsi_host_common_cfg *cfg,

				 u32 vc_id,

				 struct dsi_rect *roi);
@@ -850,6 +851,7 @@ struct dsi_ctrl_hw_ops { 
 *                          dsi controller and run only dsi controller.

 * @null_insertion_enabled:  A boolean property to allow dsi controller to

 *                           insert null packet.

 * @widebus_support:        48 bit wide data bus is supported.

 */

struct dsi_ctrl_hw {

	void __iomem *base;
@@ -870,6 +872,7 @@ struct dsi_ctrl_hw { 


	bool phy_isolation_enabled;

	bool null_insertion_enabled;

	bool widebus_support;

};



#endif /* _DSI_CTRL_HW_H_ */

msm/dsi/dsi_ctrl_hw_cmn.c

+26 −5
Original line number Diff line number Diff line
@@ -342,6 +342,16 @@ void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl, 
		reg |= eol_byte_num << 4;

		reg |= 1;

		DSI_W32(ctrl, DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);



		if (ctrl->widebus_support) {

			reg = DSI_R32(ctrl, DSI_VIDEO_MODE_CTRL);

			reg |= BIT(25);

			DSI_W32(ctrl, DSI_VIDEO_MODE_CTRL, reg);

		}



		mode->h_active = DIV_ROUND_UP(mode->h_active *

				mode->pclk_scale.numer,

				mode->pclk_scale.denom);

	} else {

		width = mode->h_active;

	}
@@ -388,14 +398,15 @@ void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl, 
 * setup_cmd_stream() - set up parameters for command pixel streams

 * @ctrl:              Pointer to controller host hardware.

 * @mode:              Pointer to mode information.

 * @h_stride:          Horizontal stride in bytes.

 * @cfg:               DSI host configuration that is common to both

 *                     video and command modes.

 * @vc_id:             stream_id

 *

 * Setup parameters for command mode pixel stream size.

 */

void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl,

				     struct dsi_mode_info *mode,

				     u32 h_stride,

				     struct dsi_host_common_cfg *cfg,

				     u32 vc_id,

				     struct dsi_rect *roi)

{
@@ -421,7 +432,7 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl, 


		sde_dsc_populate_dsc_private_params(&dsc, intf_ip_w);



		width_final = dsc.pclk_per_line;

		width_final = dsc.bytes_per_pkt * dsc.pkt_per_line;

		stride_final = dsc.bytes_per_pkt;

		pkt_per_line = dsc.pkt_per_line;

		eol_byte_num = dsc.eol_byte_num;
@@ -436,7 +447,7 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl, 


		sde_vdc_intf_prog_params(&vdc, intf_ip_w);



		width_final = vdc.pclk_per_line;

		width_final = vdc.bytes_per_pkt * vdc.pkt_per_line;

		stride_final = vdc.bytes_per_pkt;

		pkt_per_line = vdc.pkt_per_line;

		eol_byte_num = vdc.eol_byte_num;
@@ -447,13 +458,23 @@ void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl, 
		height_final = roi->h;

	} else {

		width_final = mode->h_active;

		stride_final = h_stride;

		stride_final = mode->h_active * 3;

		height_final = mode->v_active;

	}



	if (dsi_compression_enabled(mode)) {

		pic_width = roi ? roi->w : mode->h_active;

		height_final = roi ? roi->h : mode->v_active;



		if (ctrl->widebus_support) {

			width_final = DIV_ROUND_UP(width_final, 6);

			reg = DSI_R32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2);

			reg |= BIT(20);

			DSI_W32(ctrl, DSI_COMMAND_MODE_MDP_CTRL2, reg);

		} else {

			width_final = DIV_ROUND_UP(width_final, 3);

		}



		reg_ctrl = DSI_R32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL);

		reg_ctrl2 = DSI_R32(ctrl, DSI_COMMAND_COMPRESSION_MODE_CTRL2);