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Commit 5658366a authored by Jack Steiner's avatar Jack Steiner Committed by Linus Torvalds
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gru: update GRU structures to match latest hardware spec 



Add a few new definitions for chipset MMR field names.  This matches rev
0.7 of the hardware spec.

Signed-off-by: default avatarJack Steiner <steiner@sgi.com>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 41314790

drivers/misc/sgi-gru/gru_instructions.h

+4 −1
Original line number Diff line number Diff line
@@ -265,6 +265,7 @@ struct gru_instruction { 
#define CBE_CAUSE_PROTOCOL_STATE_DATA_ERROR	(1 << 16)

#define CBE_CAUSE_RA_RESPONSE_DATA_ERROR	(1 << 17)

#define CBE_CAUSE_HA_RESPONSE_DATA_ERROR	(1 << 18)

#define CBE_CAUSE_FORCED_ERROR			(1 << 19)



/* CBE cbrexecstatus bits */

#define CBR_EXS_ABORT_OCC_BIT			0
@@ -273,13 +274,15 @@ struct gru_instruction { 
#define CBR_EXS_QUEUED_BIT			3

#define CBR_EXS_TLB_INVAL_BIT			4

#define CBR_EXS_EXCEPTION_BIT			5

#define CBR_EXS_CB_INT_PENDING_BIT		6



#define CBR_EXS_ABORT_OCC			(1 << CBR_EXS_ABORT_OCC_BIT)

#define CBR_EXS_INT_OCC				(1 << CBR_EXS_INT_OCC_BIT)

#define CBR_EXS_PENDING				(1 << CBR_EXS_PENDING_BIT)

#define CBR_EXS_QUEUED				(1 << CBR_EXS_QUEUED_BIT)

#define CBR_TLB_INVAL				(1 << CBR_EXS_TLB_INVAL_BIT)

#define CBR_EXS_TLB_INVAL			(1 << CBR_EXS_TLB_INVAL_BIT)

#define CBR_EXS_EXCEPTION			(1 << CBR_EXS_EXCEPTION_BIT)

#define CBR_EXS_CB_INT_PENDING			(1 << CBR_EXS_CB_INT_PENDING_BIT)



/*

 * Exceptions are retried for the following cases. If any OTHER bits are set

drivers/misc/sgi-gru/gruhandles.h

+11 −0
Original line number Diff line number Diff line
@@ -252,6 +252,17 @@ enum gru_tgh_state { 
	TGHSTATE_RESTART_CTX,

};



enum gru_tgh_cause {

	TGHCAUSE_RR_ECC,

	TGHCAUSE_TLB_ECC,

	TGHCAUSE_LRU_ECC,

	TGHCAUSE_PS_ECC,

	TGHCAUSE_MUL_ERR,

	TGHCAUSE_DATA_ERR,

	TGHCAUSE_SW_FORCE

};





/*

 * TFH - TLB Global Handle

 * 	Used for TLB dropins into the GRU TLB.