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Commit 563493f2 authored by Qiuxu Zhuo's avatar Qiuxu Zhuo Committed by Greg Kroah-Hartman
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EDAC/ie31200: Fix the DIMM size mask for several SoCs 



[ Upstream commit 3427befbbca6b19fe0e37f91d66ce5221de70bf1 ]

The DIMM size mask for {Sky, Kaby, Coffee} Lake is not bits{7:0},
but bits{5:0}. Fix it.

Fixes: 953dee9b ("EDAC, ie31200_edac: Add Skylake support")
Signed-off-by: default avatarQiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: default avatarTony Luck <tony.luck@intel.com>
Tested-by: default avatarGary Wang <gary.c.wang@intel.com>
Link: https://lore.kernel.org/r/20250310011411.31685-3-qiuxu.zhuo@intel.com


Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent eb96456b

drivers/edac/ie31200_edac.c

+2 −1
Original line number Diff line number Diff line
@@ -154,6 +154,7 @@ 
#define IE31200_MAD_DIMM_0_OFFSET		0x5004

#define IE31200_MAD_DIMM_0_OFFSET_SKL		0x500C

#define IE31200_MAD_DIMM_SIZE			GENMASK_ULL(7, 0)

#define IE31200_MAD_DIMM_SIZE_SKL		GENMASK_ULL(5, 0)

#define IE31200_MAD_DIMM_A_RANK			BIT(17)

#define IE31200_MAD_DIMM_A_RANK_SHIFT		17

#define IE31200_MAD_DIMM_A_RANK_SKL		BIT(10)
@@ -368,7 +369,7 @@ static void __iomem *ie31200_map_mchbar(struct pci_dev *pdev) 
static void __skl_populate_dimm_info(struct dimm_data *dd, u32 addr_decode,

				     int chan)

{

	dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE;

	dd->size = (addr_decode >> (chan << 4)) & IE31200_MAD_DIMM_SIZE_SKL;

	dd->dual_rank = (addr_decode & (IE31200_MAD_DIMM_A_RANK_SKL << (chan << 4))) ? 1 : 0;

	dd->x16_width = ((addr_decode & (IE31200_MAD_DIMM_A_WIDTH_SKL << (chan << 4))) >>

				(IE31200_MAD_DIMM_A_WIDTH_SKL_SHIFT + (chan << 4)));