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Commit 55e1a5c8 authored by Linux Build Service Account's avatar Linux Build Service Account
Browse files

Merge b2e71fbd on remote branch 

Change-Id: I494533031f14846b222ccace007cdcec48b470cc
parents 72be295f b2e71fbd

drivers/char/adsprpc.c

+8 −1
Original line number Diff line number Diff line
@@ -118,6 +118,9 @@ 
#define GET_TABLE_IDX_FROM_CTXID(ctxid) \

	((ctxid & FASTRPC_CTX_TABLE_IDX_MASK) >> FASTRPC_CTX_TABLE_IDX_POS)



#define VALID_FASTRPC_CID(cid) \

	(cid >= ADSP_DOMAIN_ID && cid < NUM_CHANNELS)



/* Reserve few entries in context table for critical kernel and static RPC

 * calls to avoid user invocations from exhausting all entries.

 */
@@ -2066,7 +2069,11 @@ static int context_alloc(struct fastrpc_file *fl, uint32_t kernel, 
		if (err)

			goto bail;

	}



	VERIFY(err, VALID_FASTRPC_CID(cid));

	if (err) {

		err = -ECHRNG;

		goto bail;

	}

	chan = &me->channel[cid];



	spin_lock_irqsave(&chan->ctxlock, irq_flags);

drivers/clk/qcom/gcc-sdxlemur.c

+1 −1
Original line number Diff line number Diff line
@@ -764,7 +764,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = { 
	F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),

	F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),

	F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),

	F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),

	F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),

	{ }

};

drivers/i2c/busses/i2c-msm-geni.c

+7 −0
Original line number Diff line number Diff line
@@ -513,6 +513,13 @@ static void gi2c_gsi_rx_cb(void *ptr) 
	struct msm_gpi_dma_async_tx_cb_param *rx_cb = ptr;

	struct geni_i2c_dev *gi2c = rx_cb->userdata;



	if (gi2c->cur == NULL) {

		GENI_SE_ERR(gi2c->ipcl, true, gi2c->dev,

			"%s: Error: unexpected callback\n", __func__);

		WARN_ON(1);

		return;

	}



	if (gi2c->cur->flags & I2C_M_RD) {

		gi2c_gsi_cb_err(rx_cb, "RX");

		complete(&gi2c->xfer);

drivers/pci/controller/pci-msm.c

+24 −3
Original line number Diff line number Diff line
@@ -72,6 +72,7 @@ 
#define PCIE20_PARF_PHY_CTRL (0x40)

#define PCIE20_PARF_TEST_BUS (0xe4)

#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL (0x174)

#define PCIE20_PARF_AXI_MSTR_RD_ADDR_HALT (0x1a4)

#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT (0x1a8)

#define PCIE20_PARF_LTSSM (0x1b0)

#define PCIE20_PARF_INT_ALL_STATUS (0x224)
@@ -845,6 +846,7 @@ struct msm_pcie_dev_t { 
	uint32_t aux_clk_freq;

	bool linkdown_panic;

	uint32_t boot_option;

	bool pcie_halt_feature_dis;



	uint32_t rc_idx;

	uint32_t phy_ver;
@@ -1680,6 +1682,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->wr_halt_size);

	PCIE_DBG_FS(dev, "slv_addr_space_size: 0x%x\n",

		dev->slv_addr_space_size);

	PCIE_DBG_FS(dev, "PCIe: halt_feature_dis is %d\n",

		dev->pcie_halt_feature_dis);

	PCIE_DBG_FS(dev, "phy_status_offset: 0x%x\n",

		dev->phy_status_offset);

	PCIE_DBG_FS(dev, "phy_status_bit: %u\n",
@@ -4740,10 +4744,22 @@ static int msm_pcie_enable(struct msm_pcie_dev_t *dev) 
	msm_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE,

				dev->slv_addr_space_size);



	if (dev->pcie_halt_feature_dis) {

		/* Disable PCIe Wr halt window */

		val = readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);

		msm_pcie_write_reg(dev->parf, PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,

				(~BIT(31)) & val);



		/* Disable PCIe Rd halt window */

		val = readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_RD_ADDR_HALT);

		msm_pcie_write_reg(dev->parf, PCIE20_PARF_AXI_MSTR_RD_ADDR_HALT,

			(~BIT(0)) & val);

	} else {

		val = dev->wr_halt_size ? dev->wr_halt_size :

			readl_relaxed(dev->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT);

		msm_pcie_write_reg(dev->parf, PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,

				BIT(31) | val);

	}



	/* init tcsr */

	if (dev->tcsr_config)
@@ -6291,6 +6307,11 @@ static int msm_pcie_probe(struct platform_device *pdev) 
	PCIE_DBG(pcie_dev, "RC%d: num-parf-testbus-sel: 0x%x.\n",

		pcie_dev->rc_idx, pcie_dev->num_parf_testbus_sel);



	pcie_dev->pcie_halt_feature_dis = of_property_read_bool(of_node,

			"qcom,pcie-halt-feature-dis");

	PCIE_DBG(pcie_dev, "PCIe halt feature is %s enabled.\n",

			pcie_dev->pcie_halt_feature_dis ? "not" : "");



	of_property_read_u32(of_node, "qcom,phy-status-offset",

				&pcie_dev->phy_status_offset);

	PCIE_DBG(pcie_dev, "RC%d: phy-status-offset: 0x%x.\n", pcie_dev->rc_idx,

drivers/platform/msm/ep_pcie/ep_pcie_com.h

+1 −0
Original line number Diff line number Diff line
@@ -393,6 +393,7 @@ struct ep_pcie_dev_t { 
	ulong                        wake_counter;

	ulong                        msi_counter;

	ulong                        global_irq_counter;

	ulong                        perst_ast_in_enum_counter;



	bool                         dump_conf;

	bool                         config_mmio_init;