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Unverified Commit 55b407f6 authored by Vasily Khoruzhick's avatar Vasily Khoruzhick Committed by Mark Brown
Browse files

ASoC: sun8i-codec-analog: split regmap code into separate driver 



It will be reused by sun50i-codec-analog later.

Signed-off-by: default avatarVasily Khoruzhick <anarsoul@gmail.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent 13c3bf17

sound/soc/sunxi/Kconfig

+6 −1
Original line number Diff line number Diff line
@@ -23,7 +23,7 @@ config SND_SUN8I_CODEC 
config SND_SUN8I_CODEC_ANALOG

	tristate "Allwinner sun8i Codec Analog Controls Support"

	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST

	select REGMAP

	select SND_SUN8I_ADDA_PR_REGMAP

	help

	  Say Y or M if you want to add support for the analog controls for

	  the codec embedded in newer Allwinner SoCs.
@@ -45,4 +45,9 @@ config SND_SUN4I_SPDIF 
	help

	  Say Y or M to add support for the S/PDIF audio block in the Allwinner

	  A10 and affiliated SoCs.



config SND_SUN8I_ADDA_PR_REGMAP

	tristate

	select REGMAP



endmenu

sound/soc/sunxi/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -4,3 +4,4 @@ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o 
obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o

obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o

obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o

obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o

sound/soc/sunxi/sun8i-adda-pr-regmap.c

0 → 100644
+102 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0+

/*

 * This driver provides regmap to access to analog part of audio codec

 * found on Allwinner A23, A31s, A33, H3 and A64 Socs

 *

 * Copyright 2016 Chen-Yu Tsai <wens@csie.org>

 * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>

 */



#include <linux/io.h>

#include <linux/kernel.h>

#include <linux/module.h>

#include <linux/regmap.h>



#include "sun8i-adda-pr-regmap.h"



/* Analog control register access bits */

#define ADDA_PR			0x0		/* PRCM base + 0x1c0 */

#define ADDA_PR_RESET			BIT(28)

#define ADDA_PR_WRITE			BIT(24)

#define ADDA_PR_ADDR_SHIFT		16

#define ADDA_PR_ADDR_MASK		GENMASK(4, 0)

#define ADDA_PR_DATA_IN_SHIFT		8

#define ADDA_PR_DATA_IN_MASK		GENMASK(7, 0)

#define ADDA_PR_DATA_OUT_SHIFT		0

#define ADDA_PR_DATA_OUT_MASK		GENMASK(7, 0)



/* regmap access bits */

static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)

{

	void __iomem *base = (void __iomem *)context;

	u32 tmp;



	/* De-assert reset */

	writel(readl(base) | ADDA_PR_RESET, base);



	/* Clear write bit */

	writel(readl(base) & ~ADDA_PR_WRITE, base);



	/* Set register address */

	tmp = readl(base);

	tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);

	tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;

	writel(tmp, base);



	/* Read back value */

	*val = readl(base) & ADDA_PR_DATA_OUT_MASK;



	return 0;

}



static int adda_reg_write(void *context, unsigned int reg, unsigned int val)

{

	void __iomem *base = (void __iomem *)context;

	u32 tmp;



	/* De-assert reset */

	writel(readl(base) | ADDA_PR_RESET, base);



	/* Set register address */

	tmp = readl(base);

	tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);

	tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;

	writel(tmp, base);



	/* Set data to write */

	tmp = readl(base);

	tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);

	tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;

	writel(tmp, base);



	/* Set write bit to signal a write */

	writel(readl(base) | ADDA_PR_WRITE, base);



	/* Clear write bit */

	writel(readl(base) & ~ADDA_PR_WRITE, base);



	return 0;

}



static const struct regmap_config adda_pr_regmap_cfg = {

	.name		= "adda-pr",

	.reg_bits	= 5,

	.reg_stride	= 1,

	.val_bits	= 8,

	.reg_read	= adda_reg_read,

	.reg_write	= adda_reg_write,

	.fast_io	= true,

	.max_register	= 31,

};



struct regmap *sun8i_adda_pr_regmap_init(struct device *dev,

					 void __iomem *base)

{

	return devm_regmap_init(dev, NULL, base, &adda_pr_regmap_cfg);

}

EXPORT_SYMBOL_GPL(sun8i_adda_pr_regmap_init);



MODULE_DESCRIPTION("Allwinner analog audio codec regmap driver");

MODULE_AUTHOR("Vasily Khoruzhick <anarsoul@gmail.com>");

MODULE_LICENSE("GPL");

MODULE_ALIAS("platform:sunxi-adda-pr");

sound/soc/sunxi/sun8i-adda-pr-regmap.h

0 → 100644
+7 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0+ */

/*

 * Copyright (C) 2018 Vasily Khoruzhick <anarsoul@gmail.com>

 */



struct regmap *sun8i_adda_pr_regmap_init(struct device *dev,

					 void __iomem *base);

sound/soc/sunxi/sun8i-codec-analog.c

+3 −76
Original line number Diff line number Diff line
@@ -27,6 +27,8 @@ 
#include <sound/soc-dapm.h>

#include <sound/tlv.h>



#include "sun8i-adda-pr-regmap.h"



/* Codec analog control register offsets and bit fields */

#define SUN8I_ADDA_HP_VOLC		0x00

#define SUN8I_ADDA_HP_VOLC_PA_CLK_GATE		7
@@ -120,81 +122,6 @@ 
#define SUN8I_ADDA_ADC_AP_EN_ADCLEN		6

#define SUN8I_ADDA_ADC_AP_EN_ADCG		0



/* Analog control register access bits */

#define ADDA_PR			0x0		/* PRCM base + 0x1c0 */

#define ADDA_PR_RESET			BIT(28)

#define ADDA_PR_WRITE			BIT(24)

#define ADDA_PR_ADDR_SHIFT		16

#define ADDA_PR_ADDR_MASK		GENMASK(4, 0)

#define ADDA_PR_DATA_IN_SHIFT		8

#define ADDA_PR_DATA_IN_MASK		GENMASK(7, 0)

#define ADDA_PR_DATA_OUT_SHIFT		0

#define ADDA_PR_DATA_OUT_MASK		GENMASK(7, 0)



/* regmap access bits */

static int adda_reg_read(void *context, unsigned int reg, unsigned int *val)

{

	void __iomem *base = (void __iomem *)context;

	u32 tmp;



	/* De-assert reset */

	writel(readl(base) | ADDA_PR_RESET, base);



	/* Clear write bit */

	writel(readl(base) & ~ADDA_PR_WRITE, base);



	/* Set register address */

	tmp = readl(base);

	tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);

	tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;

	writel(tmp, base);



	/* Read back value */

	*val = readl(base) & ADDA_PR_DATA_OUT_MASK;



	return 0;

}



static int adda_reg_write(void *context, unsigned int reg, unsigned int val)

{

	void __iomem *base = (void __iomem *)context;

	u32 tmp;



	/* De-assert reset */

	writel(readl(base) | ADDA_PR_RESET, base);



	/* Set register address */

	tmp = readl(base);

	tmp &= ~(ADDA_PR_ADDR_MASK << ADDA_PR_ADDR_SHIFT);

	tmp |= (reg & ADDA_PR_ADDR_MASK) << ADDA_PR_ADDR_SHIFT;

	writel(tmp, base);



	/* Set data to write */

	tmp = readl(base);

	tmp &= ~(ADDA_PR_DATA_IN_MASK << ADDA_PR_DATA_IN_SHIFT);

	tmp |= (val & ADDA_PR_DATA_IN_MASK) << ADDA_PR_DATA_IN_SHIFT;

	writel(tmp, base);



	/* Set write bit to signal a write */

	writel(readl(base) | ADDA_PR_WRITE, base);



	/* Clear write bit */

	writel(readl(base) & ~ADDA_PR_WRITE, base);



	return 0;

}



static const struct regmap_config adda_pr_regmap_cfg = {

	.name		= "adda-pr",

	.reg_bits	= 5,

	.reg_stride	= 1,

	.val_bits	= 8,

	.reg_read	= adda_reg_read,

	.reg_write	= adda_reg_write,

	.fast_io	= true,

	.max_register	= 24,

};



/* mixer controls */

static const struct snd_kcontrol_new sun8i_codec_mixer_controls[] = {

	SOC_DAPM_DOUBLE_R("DAC Playback Switch",
@@ -912,7 +839,7 @@ static int sun8i_codec_analog_probe(struct platform_device *pdev) 
		return PTR_ERR(base);

	}



	regmap = devm_regmap_init(&pdev->dev, NULL, base, &adda_pr_regmap_cfg);

	regmap = sun8i_adda_pr_regmap_init(&pdev->dev, base);

	if (IS_ERR(regmap)) {

		dev_err(&pdev->dev, "Failed to create regmap\n");

		return PTR_ERR(regmap);