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Commit 5502bef3 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'mlx5e-100G-extensions' 



Saeed Mahameed says:

====================
Mellanox 100G mlx5e Ethernet extensions

This series includes multiple features extensions for mlx5 Ethernet netdevice driver.
Namely, TX Rate limiting, RX interrupt moderation, ethtool settings.

TX Rate limiting:
	- ConnectX-4 rate limiting infrastructure
	- Set max rate NDO support

RX interrupt moderation:
	- CQE based coalescing option (controlled via priv flags)
	- Adaptive RX coalescing

ethtool settings:
	- priv flags callbacks
	- Support new ksettings API
	- Add 50G missing link mode
	- Support auto negotiation on/off

Applied on top: 0e9390eb ("Merge branch 'mlxsw-next'")
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents f1eecb7e 52244d96

drivers/net/ethernet/mellanox/mlx5/core/Makefile

+5 −3
Original line number Diff line number Diff line
@@ -2,10 +2,12 @@ obj-$(CONFIG_MLX5_CORE) += mlx5_core.o 


mlx5_core-y :=	main.o cmd.o debugfs.o fw.o eq.o uar.o pagealloc.o \

		health.o mcg.o cq.o srq.o alloc.o qp.o port.o mr.o pd.o \

		mad.o transobj.o vport.o sriov.o fs_cmd.o fs_core.o fs_counters.o

		mad.o transobj.o vport.o sriov.o fs_cmd.o fs_core.o \

		fs_counters.o rl.o



mlx5_core-$(CONFIG_MLX5_CORE_EN) += wq.o eswitch.o \

		en_main.o en_fs.o en_ethtool.o en_tx.o en_rx.o \

		en_txrx.o en_clock.o vxlan.o en_tc.o en_arfs.o

		en_rx_am.o en_txrx.o en_clock.o vxlan.o en_tc.o \

		en_arfs.o



mlx5_core-$(CONFIG_MLX5_CORE_EN_DCB) +=  en_dcbnl.o

drivers/net/ethernet/mellanox/mlx5/core/en.h

+69 −4
Original line number Diff line number Diff line
@@ -79,6 +79,7 @@ 


#define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ                 (64 * 1024)

#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC      0x10

#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3

#define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS      0x20

#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC      0x10

#define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS      0x20
@@ -88,6 +89,7 @@ 
#define MLX5E_LOG_INDIR_RQT_SIZE       0x7

#define MLX5E_INDIR_RQT_SIZE           BIT(MLX5E_LOG_INDIR_RQT_SIZE)

#define MLX5E_MAX_NUM_CHANNELS         (MLX5E_INDIR_RQT_SIZE >> 1)

#define MLX5E_MAX_NUM_SQS              (MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC)

#define MLX5E_TX_CQ_POLL_BUDGET        128

#define MLX5E_UPDATE_STATS_INTERVAL    200 /* msecs */

#define MLX5E_SQ_BF_BUDGET             16
@@ -143,11 +145,32 @@ struct mlx5e_umr_wqe { 
	struct mlx5_wqe_data_seg       data;

};



static const char mlx5e_priv_flags[][ETH_GSTRING_LEN] = {

	"rx_cqe_moder",

};



enum mlx5e_priv_flag {

	MLX5E_PFLAG_RX_CQE_BASED_MODER = (1 << 0),

};



#define MLX5E_SET_PRIV_FLAG(priv, pflag, enable)    \

	do {                                        \

		if (enable)                         \

			priv->pflags |= pflag;      \

		else                                \

			priv->pflags &= ~pflag;     \

	} while (0)



#ifdef CONFIG_MLX5_CORE_EN_DCB

#define MLX5E_MAX_BW_ALLOC 100 /* Max percentage of BW allocation */

#define MLX5E_MIN_BW_ALLOC 1   /* Min percentage of BW allocation */

#endif



struct mlx5e_cq_moder {

	u16 usec;

	u16 pkts;

};



struct mlx5e_params {

	u8  log_sq_size;

	u8  rq_wq_type;
@@ -156,12 +179,11 @@ struct mlx5e_params { 
	u8  log_rq_size;

	u16 num_channels;

	u8  num_tc;

	u8  rx_cq_period_mode;

	bool rx_cqe_compress_admin;

	bool rx_cqe_compress;

	u16 rx_cq_moderation_usec;

	u16 rx_cq_moderation_pkts;

	u16 tx_cq_moderation_usec;

	u16 tx_cq_moderation_pkts;

	struct mlx5e_cq_moder rx_cq_moderation;

	struct mlx5e_cq_moder tx_cq_moderation;

	u16 min_rx_wqes;

	bool lro_en;

	u32 lro_wqe_sz;
@@ -173,6 +195,7 @@ struct mlx5e_params { 
#ifdef CONFIG_MLX5_CORE_EN_DCB

	struct ieee_ets ets;

#endif

	bool rx_am_enabled;

};



struct mlx5e_tstamp {
@@ -191,6 +214,7 @@ struct mlx5e_tstamp { 
enum {

	MLX5E_RQ_STATE_POST_WQES_ENABLE,

	MLX5E_RQ_STATE_UMR_WQE_IN_PROGRESS,

	MLX5E_RQ_STATE_AM,

};



struct mlx5e_cq {
@@ -198,6 +222,7 @@ struct mlx5e_cq { 
	struct mlx5_cqwq           wq;



	/* data path - accessed per napi poll */

	u16                        event_ctr;

	struct napi_struct        *napi;

	struct mlx5_core_cq        mcq;

	struct mlx5e_channel      *channel;
@@ -225,6 +250,30 @@ struct mlx5e_dma_info { 
	dma_addr_t	addr;

};



struct mlx5e_rx_am_stats {

	int ppms; /* packets per msec */

	int epms; /* events per msec */

};



struct mlx5e_rx_am_sample {

	ktime_t		time;

	unsigned int	pkt_ctr;

	u16		event_ctr;

};



struct mlx5e_rx_am { /* Adaptive Moderation */

	u8					state;

	struct mlx5e_rx_am_stats		prev_stats;

	struct mlx5e_rx_am_sample		start_sample;

	struct work_struct			work;

	u8					profile_ix;

	u8					mode;

	u8					tune_state;

	u8					steps_right;

	u8					steps_left;

	u8					tired;

};



struct mlx5e_rq {

	/* data path */

	struct mlx5_wq_ll      wq;
@@ -245,6 +294,8 @@ struct mlx5e_rq { 
	unsigned long          state;

	int                    ix;



	struct mlx5e_rx_am     am; /* Adaptive Moderation */



	/* control */

	struct mlx5_wq_ctrl    wq_ctrl;

	u8                     wq_type;
@@ -354,6 +405,7 @@ struct mlx5e_sq { 
	struct mlx5e_channel      *channel;

	int                        tc;

	struct mlx5e_ico_wqe_info *ico_wqe_info;

	u32                        rate_limit;

} ____cacheline_aligned_in_smp;



static inline bool mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
@@ -530,6 +582,7 @@ struct mlx5e_priv { 
	u32                        indir_rqtn;

	u32                        indir_tirn[MLX5E_NUM_INDIR_TIRS];

	struct mlx5e_direct_tir    direct_tir[MLX5E_MAX_NUM_CHANNELS];

	u32                        tx_rates[MLX5E_MAX_NUM_SQS];



	struct mlx5e_flow_steering fs;

	struct mlx5e_vxlan_db      vxlan;
@@ -540,6 +593,7 @@ struct mlx5e_priv { 
	struct work_struct         set_rx_mode_work;

	struct delayed_work        update_stats_work;



	u32                        pflags;

	struct mlx5_core_dev      *mdev;

	struct net_device         *netdev;

	struct mlx5e_stats         stats;
@@ -562,6 +616,7 @@ enum mlx5e_link_mode { 
	MLX5E_10GBASE_ER	 = 14,

	MLX5E_40GBASE_SR4	 = 15,

	MLX5E_40GBASE_LR4	 = 16,

	MLX5E_50GBASE_SR2	 = 18,

	MLX5E_100GBASE_CR4	 = 20,

	MLX5E_100GBASE_SR4	 = 21,

	MLX5E_100GBASE_KR4	 = 22,
@@ -579,6 +634,9 @@ enum mlx5e_link_mode { 


#define MLX5E_PROT_MASK(link_mode) (1 << link_mode)





void mlx5e_build_ptys2ethtool_map(void);



void mlx5e_send_nop(struct mlx5e_sq *sq, bool notify_hw);

u16 mlx5e_select_queue(struct net_device *dev, struct sk_buff *skb,

		       void *accel_priv, select_queue_fallback_t fallback);
@@ -612,6 +670,10 @@ void mlx5e_free_rx_fragmented_mpwqe(struct mlx5e_rq *rq, 
				    struct mlx5e_mpw_info *wi);

struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);



void mlx5e_rx_am(struct mlx5e_rq *rq);

void mlx5e_rx_am_work(struct work_struct *work);

struct mlx5e_cq_moder mlx5e_am_get_def_profile(u8 rx_cq_period_mode);



void mlx5e_update_stats(struct mlx5e_priv *priv);



int mlx5e_create_flow_steering(struct mlx5e_priv *priv);
@@ -647,6 +709,9 @@ void mlx5e_build_default_indir_rqt(struct mlx5_core_dev *mdev, 
				   int num_channels);

int mlx5e_get_max_linkspeed(struct mlx5_core_dev *mdev, u32 *speed);



void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params,

				 u8 cq_period_mode);



static inline void mlx5e_tx_notify_hw(struct mlx5e_sq *sq,

				      struct mlx5_wqe_ctrl_seg *ctrl, int bf_sz)

{

drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c

+1 −8
Original line number Diff line number Diff line
@@ -191,7 +191,6 @@ static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev, 
{

	struct mlx5e_priv *priv = netdev_priv(dev);

	struct mlx5_core_dev *mdev = priv->mdev;

	enum mlx5_port_status ps;

	u8 curr_pfc_en;

	int ret;
@@ -200,14 +199,8 @@ static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev, 
	if (pfc->pfc_en == curr_pfc_en)

		return 0;



	mlx5_query_port_admin_status(mdev, &ps);

	if (ps == MLX5_PORT_UP)

		mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);



	ret = mlx5_set_port_pfc(mdev, pfc->pfc_en, pfc->pfc_en);



	if (ps == MLX5_PORT_UP)

		mlx5_set_port_admin_status(mdev, MLX5_PORT_UP);

	mlx5_toggle_port_link(mdev);



	return ret;

}

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

+287 −189

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/mellanox/mlx5/core/en_main.c

+161 −20
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ 
struct mlx5e_rq_param {

	u32			rqc[MLX5_ST_SZ_DW(rqc)];

	struct mlx5_wq_param	wq;

	bool			am_enabled;

};



struct mlx5e_sq_param {
@@ -55,6 +56,7 @@ struct mlx5e_cq_param { 
	u32                        cqc[MLX5_ST_SZ_DW(cqc)];

	struct mlx5_wq_param       wq;

	u16                        eq_ix;

	u8                         cq_period_mode;

};



struct mlx5e_channel_param {
@@ -336,6 +338,9 @@ static int mlx5e_create_rq(struct mlx5e_channel *c, 
		wqe->data.byte_count = cpu_to_be32(byte_count);

	}



	INIT_WORK(&rq->am.work, mlx5e_rx_am_work);

	rq->am.mode = priv->params.rx_cq_period_mode;



	rq->wq_type = priv->params.rq_wq_type;

	rq->pdev    = c->pdev;

	rq->netdev  = c->netdev;
@@ -508,6 +513,9 @@ static int mlx5e_open_rq(struct mlx5e_channel *c, 
	if (err)

		goto err_disable_rq;



	if (param->am_enabled)

		set_bit(MLX5E_RQ_STATE_AM, &c->rq.state);



	set_bit(MLX5E_RQ_STATE_POST_WQES_ENABLE, &rq->state);



	sq->ico_wqe_info[pi].opcode     = MLX5_OPCODE_NOP;
@@ -536,6 +544,8 @@ static void mlx5e_close_rq(struct mlx5e_rq *rq) 
	/* avoid destroying rq before mlx5e_poll_rx_cq() is done with it */

	napi_synchronize(&rq->channel->napi);



	cancel_work_sync(&rq->am.work);



	mlx5e_disable_rq(rq);

	mlx5e_destroy_rq(rq);

}
@@ -702,7 +712,8 @@ static int mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param) 
	return err;

}



static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)

static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state,

			   int next_state, bool update_rl, int rl_index)

{

	struct mlx5e_channel *c = sq->channel;

	struct mlx5e_priv *priv = c->priv;
@@ -722,6 +733,10 @@ static int mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state) 


	MLX5_SET(modify_sq_in, in, sq_state, curr_state);

	MLX5_SET(sqc, sqc, state, next_state);

	if (update_rl && next_state == MLX5_SQC_STATE_RDY) {

		MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);

		MLX5_SET(sqc,  sqc, packet_pacing_rate_limit_index, rl_index);

	}



	err = mlx5_core_modify_sq(mdev, sq->sqn, in, inlen);
@@ -737,6 +752,8 @@ static void mlx5e_disable_sq(struct mlx5e_sq *sq) 
	struct mlx5_core_dev *mdev = priv->mdev;



	mlx5_core_destroy_sq(mdev, sq->sqn);

	if (sq->rate_limit)

		mlx5_rl_remove_rate(mdev, sq->rate_limit);

}



static int mlx5e_open_sq(struct mlx5e_channel *c,
@@ -754,7 +771,8 @@ static int mlx5e_open_sq(struct mlx5e_channel *c, 
	if (err)

		goto err_destroy_sq;



	err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);

	err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY,

			      false, 0);

	if (err)

		goto err_disable_sq;
@@ -793,7 +811,8 @@ static void mlx5e_close_sq(struct mlx5e_sq *sq) 
		if (mlx5e_sq_has_room_for(sq, 1))

			mlx5e_send_nop(sq, true);



		mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);

		mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR,

				false, 0);

	}



	while (sq->cc != sq->pc) /* wait till sq is empty */
@@ -887,6 +906,7 @@ static int mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param) 


	mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);



	MLX5_SET(cqc,   cqc, cq_period_mode, param->cq_period_mode);

	MLX5_SET(cqc,   cqc, c_eqn,         eqn);

	MLX5_SET(cqc,   cqc, uar_page,      mcq->uar->index);

	MLX5_SET(cqc,   cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
@@ -916,8 +936,7 @@ static void mlx5e_disable_cq(struct mlx5e_cq *cq) 
static int mlx5e_open_cq(struct mlx5e_channel *c,

			 struct mlx5e_cq_param *param,

			 struct mlx5e_cq *cq,

			 u16 moderation_usecs,

			 u16 moderation_frames)

			 struct mlx5e_cq_moder moderation)

{

	int err;

	struct mlx5e_priv *priv = c->priv;
@@ -933,8 +952,8 @@ static int mlx5e_open_cq(struct mlx5e_channel *c, 


	if (MLX5_CAP_GEN(mdev, cq_moderation))

		mlx5_core_modify_cq_moderation(mdev, &cq->mcq,

					       moderation_usecs,

					       moderation_frames);

					       moderation.usec,

					       moderation.pkts);

	return 0;



err_destroy_cq:
@@ -963,8 +982,7 @@ static int mlx5e_open_tx_cqs(struct mlx5e_channel *c, 


	for (tc = 0; tc < c->num_tc; tc++) {

		err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,

				    priv->params.tx_cq_moderation_usec,

				    priv->params.tx_cq_moderation_pkts);

				    priv->params.tx_cq_moderation);

		if (err)

			goto err_close_tx_cqs;

	}
@@ -1024,14 +1042,91 @@ static void mlx5e_build_channeltc_to_txq_map(struct mlx5e_priv *priv, int ix) 
			ix + i * priv->params.num_channels;

}



static int mlx5e_set_sq_maxrate(struct net_device *dev,

				struct mlx5e_sq *sq, u32 rate)

{

	struct mlx5e_priv *priv = netdev_priv(dev);

	struct mlx5_core_dev *mdev = priv->mdev;

	u16 rl_index = 0;

	int err;



	if (rate == sq->rate_limit)

		/* nothing to do */

		return 0;



	if (sq->rate_limit)

		/* remove current rl index to free space to next ones */

		mlx5_rl_remove_rate(mdev, sq->rate_limit);



	sq->rate_limit = 0;



	if (rate) {

		err = mlx5_rl_add_rate(mdev, rate, &rl_index);

		if (err) {

			netdev_err(dev, "Failed configuring rate %u: %d\n",

				   rate, err);

			return err;

		}

	}



	err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY,

			      MLX5_SQC_STATE_RDY, true, rl_index);

	if (err) {

		netdev_err(dev, "Failed configuring rate %u: %d\n",

			   rate, err);

		/* remove the rate from the table */

		if (rate)

			mlx5_rl_remove_rate(mdev, rate);

		return err;

	}



	sq->rate_limit = rate;

	return 0;

}



static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)

{

	struct mlx5e_priv *priv = netdev_priv(dev);

	struct mlx5_core_dev *mdev = priv->mdev;

	struct mlx5e_sq *sq = priv->txq_to_sq_map[index];

	int err = 0;



	if (!mlx5_rl_is_supported(mdev)) {

		netdev_err(dev, "Rate limiting is not supported on this device\n");

		return -EINVAL;

	}



	/* rate is given in Mb/sec, HW config is in Kb/sec */

	rate = rate << 10;



	/* Check whether rate in valid range, 0 is always valid */

	if (rate && !mlx5_rl_is_in_range(mdev, rate)) {

		netdev_err(dev, "TX rate %u, is not in range\n", rate);

		return -ERANGE;

	}



	mutex_lock(&priv->state_lock);

	if (test_bit(MLX5E_STATE_OPENED, &priv->state))

		err = mlx5e_set_sq_maxrate(dev, sq, rate);

	if (!err)

		priv->tx_rates[index] = rate;

	mutex_unlock(&priv->state_lock);



	return err;

}



static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,

			      struct mlx5e_channel_param *cparam,

			      struct mlx5e_channel **cp)

{

	struct mlx5e_cq_moder icosq_cq_moder = {0, 0};

	struct net_device *netdev = priv->netdev;

	struct mlx5e_cq_moder rx_cq_profile;

	int cpu = mlx5e_get_cpu(priv, ix);

	struct mlx5e_channel *c;

	struct mlx5e_sq *sq;

	int err;

	int i;



	c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));

	if (!c)
@@ -1045,11 +1140,16 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 
	c->mkey_be  = cpu_to_be32(priv->mkey.key);

	c->num_tc   = priv->params.num_tc;



	if (priv->params.rx_am_enabled)

		rx_cq_profile = mlx5e_am_get_def_profile(priv->params.rx_cq_period_mode);

	else

		rx_cq_profile = priv->params.rx_cq_moderation;



	mlx5e_build_channeltc_to_txq_map(priv, ix);



	netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);



	err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, 0, 0);

	err = mlx5e_open_cq(c, &cparam->icosq_cq, &c->icosq.cq, icosq_cq_moder);

	if (err)

		goto err_napi_del;
@@ -1058,8 +1158,7 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 
		goto err_close_icosq_cq;



	err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,

			    priv->params.rx_cq_moderation_usec,

			    priv->params.rx_cq_moderation_pkts);

			    rx_cq_profile);

	if (err)

		goto err_close_tx_cqs;
@@ -1073,6 +1172,16 @@ static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix, 
	if (err)

		goto err_close_icosq;



	for (i = 0; i < priv->params.num_tc; i++) {

		u32 txq_ix = priv->channeltc_to_txq_map[ix][i];



		if (priv->tx_rates[txq_ix]) {

			sq = priv->txq_to_sq_map[txq_ix];

			mlx5e_set_sq_maxrate(priv->netdev, sq,

					     priv->tx_rates[txq_ix]);

		}

	}



	err = mlx5e_open_rq(c, &cparam->rq, &c->rq);

	if (err)

		goto err_close_sqs;
@@ -1149,6 +1258,8 @@ static void mlx5e_build_rq_param(struct mlx5e_priv *priv, 


	param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);

	param->wq.linear = 1;



	param->am_enabled = priv->params.rx_am_enabled;

}



static void mlx5e_build_drop_rq_param(struct mlx5e_rq_param *param)
@@ -1214,6 +1325,8 @@ static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv, 
	}



	mlx5e_build_common_cq_param(priv, param);



	param->cq_period_mode = priv->params.rx_cq_period_mode;

}



static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
@@ -1224,6 +1337,8 @@ static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv, 
	MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);



	mlx5e_build_common_cq_param(priv, param);



	param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;

}



static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
@@ -1235,6 +1350,8 @@ static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv, 
	MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);



	mlx5e_build_common_cq_param(priv, param);



	param->cq_period_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;

}



static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
@@ -2611,6 +2728,7 @@ static const struct net_device_ops mlx5e_netdev_ops_basic = { 
	.ndo_set_features        = mlx5e_set_features,

	.ndo_change_mtu          = mlx5e_change_mtu,

	.ndo_do_ioctl            = mlx5e_ioctl,

	.ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,

#ifdef CONFIG_RFS_ACCEL

	.ndo_rx_flow_steer	 = mlx5e_rx_flow_steer,

#endif
@@ -2632,6 +2750,7 @@ static const struct net_device_ops mlx5e_netdev_ops_sriov = { 
	.ndo_do_ioctl            = mlx5e_ioctl,

	.ndo_udp_tunnel_add	 = mlx5e_add_vxlan_port,

	.ndo_udp_tunnel_del	 = mlx5e_del_vxlan_port,

	.ndo_set_tx_maxrate      = mlx5e_set_tx_maxrate,

	.ndo_features_check      = mlx5e_features_check,

#ifdef CONFIG_RFS_ACCEL

	.ndo_rx_flow_steer	 = mlx5e_rx_flow_steer,
@@ -2760,6 +2879,20 @@ static bool cqe_compress_heuristic(u32 link_speed, u32 pci_bw) 
		(pci_bw < 40000) && (pci_bw < link_speed));

}



void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)

{

	params->rx_cq_period_mode = cq_period_mode;



	params->rx_cq_moderation.pkts =

		MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;

	params->rx_cq_moderation.usec =

			MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;



	if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)

		params->rx_cq_moderation.usec =

			MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;

}



static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev,

				    struct net_device *netdev,

				    int num_channels)
@@ -2767,6 +2900,9 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, 
	struct mlx5e_priv *priv = netdev_priv(netdev);

	u32 link_speed = 0;

	u32 pci_bw = 0;

	u8 cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?

					 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :

					 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;



	priv->params.log_sq_size           =

		MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
@@ -2812,13 +2948,13 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, 


	priv->params.min_rx_wqes = mlx5_min_rx_wqes(priv->params.rq_wq_type,

					    BIT(priv->params.log_rq_size));

	priv->params.rx_cq_moderation_usec =

		MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;

	priv->params.rx_cq_moderation_pkts =

		MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;

	priv->params.tx_cq_moderation_usec =



	priv->params.rx_am_enabled = MLX5_CAP_GEN(mdev, cq_moderation);

	mlx5e_set_rx_cq_mode_params(&priv->params, cq_period_mode);



	priv->params.tx_cq_moderation.usec =

		MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;

	priv->params.tx_cq_moderation_pkts =

	priv->params.tx_cq_moderation.pkts =

		MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;

	priv->params.tx_max_inline         = mlx5e_get_max_inline_cap(mdev);

	priv->params.num_tc                = 1;
@@ -2833,6 +2969,10 @@ static void mlx5e_build_netdev_priv(struct mlx5_core_dev *mdev, 
	priv->params.lro_wqe_sz            =

		MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;



	/* Initialize pflags */

	MLX5E_SET_PRIV_FLAG(priv, MLX5E_PFLAG_RX_CQE_BASED_MODER,

			    priv->params.rx_cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE);



	priv->mdev                         = mdev;

	priv->netdev                       = netdev;

	priv->params.num_channels          = num_channels;
@@ -3240,6 +3380,7 @@ static struct mlx5_interface mlx5e_interface = { 


void mlx5e_init(void)

{

	mlx5e_build_ptys2ethtool_map();

	mlx5_register_interface(&mlx5e_interface);

}