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Commit 54f4dde8 authored by Ilpo Järvinen's avatar Ilpo Järvinen Committed by Greg Kroah-Hartman
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PCI: tegra194: Use FIELD_GET()/FIELD_PREP() with Link Width fields 

[ Upstream commit 759574abd78e3b47ec45bbd31a64e8832cf73f97 ]

Use FIELD_GET() to extract PCIe Negotiated Link Width field instead of
custom masking and shifting.

Similarly, change custom code that misleadingly used
PCI_EXP_LNKSTA_NLW_SHIFT to prepare value for PCI_EXP_LNKCAP write
to use FIELD_PREP() with correct field define (PCI_EXP_LNKCAP_MLW).

Link: https://lore.kernel.org/r/20230919125648.1920-5-ilpo.jarvinen@linux.intel.com


Signed-off-by: default avatarIlpo Järvinen <ilpo.jarvinen@linux.intel.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 25277756

drivers/pci/controller/dwc/pcie-tegra194.c

+4 −5
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ 
 * Author: Vidya Sagar <vidyas@nvidia.com>

 */



#include <linux/bitfield.h>

#include <linux/clk.h>

#include <linux/debugfs.h>

#include <linux/delay.h>
@@ -321,8 +322,7 @@ static void apply_bad_link_workaround(struct pcie_port *pp) 
	 */

	val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA);

	if (val & PCI_EXP_LNKSTA_LBMS) {

		current_link_width = (val & PCI_EXP_LNKSTA_NLW) >>

				     PCI_EXP_LNKSTA_NLW_SHIFT;

		current_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);

		if (pcie->init_link_width > current_link_width) {

			dev_warn(pci->dev, "PCIe link is bad, width reduced\n");

			val = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
@@ -596,8 +596,7 @@ static void tegra_pcie_enable_system_interrupts(struct pcie_port *pp) 


	val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +

				  PCI_EXP_LNKSTA);

	pcie->init_link_width = (val_w & PCI_EXP_LNKSTA_NLW) >>

				PCI_EXP_LNKSTA_NLW_SHIFT;

	pcie->init_link_width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val_w);



	val_w = dw_pcie_readw_dbi(&pcie->pci, pcie->pcie_cap_base +

				  PCI_EXP_LNKCTL);
@@ -773,7 +772,7 @@ static void tegra_pcie_prepare_host(struct pcie_port *pp) 
	/* Configure Max lane width from DT */

	val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);

	val &= ~PCI_EXP_LNKCAP_MLW;

	val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);

	val |= FIELD_PREP(PCI_EXP_LNKCAP_MLW, pcie->num_lanes);

	dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);



	config_gen3_gen4_eq_presets(pcie);