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Commit 54d7a20d authored by Douglas Anderson's avatar Douglas Anderson Committed by Andy Gross
Browse files

arm64: dts: qcom: sdm845: Sort nodes in the soc by address 



This is pure-churn and should be a no-op.  I'm doing it in the hopes
of reducing merge conflicts.  When things are sorted in a sane way
(and by base address seems sane) then it's less likely that future
patches will cause merge conflicts.

Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Acked-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarAndy Gross <andy.gross@linaro.org>
parent 2da52398

arch/arm64/boot/dts/qcom/sdm845.dtsi

+48 −48
Original line number Diff line number Diff line
@@ -198,6 +198,54 @@ 
		ranges = <0 0 0 0xffffffff>;

		compatible = "simple-bus";



		gcc: clock-controller@100000 {

			compatible = "qcom,gcc-sdm845";

			reg = <0x100000 0x1f0000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		tcsr_mutex_regs: syscon@1f40000 {

			compatible = "syscon";

			reg = <0x1f40000 0x40000>;

		};



		tlmm: pinctrl@3400000 {

			compatible = "qcom,sdm845-pinctrl";

			reg = <0x03400000 0xc00000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		spmi_bus: spmi@c440000 {

			compatible = "qcom,spmi-pmic-arb";

			reg = <0xc440000 0x1100>,

			      <0xc600000 0x2000000>,

			      <0xe600000 0x100000>,

			      <0xe700000 0xa0000>,

			      <0xc40a000 0x26000>;

			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

			interrupt-names = "periph_irq";

			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ee = <0>;

			qcom,channel = <0>;

			#address-cells = <2>;

			#size-cells = <0>;

			interrupt-controller;

			#interrupt-cells = <4>;

			cell-index = <0>;

		};



		apss_shared: mailbox@17990000 {

			compatible = "qcom,sdm845-apss-shared";

			reg = <0x17990000 0x1000>;

			#mbox-cells = <1>;

		};



		intc: interrupt-controller@17a00000 {

			compatible = "arm,gic-v3";

			#address-cells = <1>;
@@ -218,24 +266,6 @@ 
			};

		};



		gcc: clock-controller@100000 {

			compatible = "qcom,gcc-sdm845";

			reg = <0x100000 0x1f0000>;

			#clock-cells = <1>;

			#reset-cells = <1>;

			#power-domain-cells = <1>;

		};



		tlmm: pinctrl@3400000 {

			compatible = "qcom,sdm845-pinctrl";

			reg = <0x03400000 0xc00000>;

			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;

			gpio-controller;

			#gpio-cells = <2>;

			interrupt-controller;

			#interrupt-cells = <2>;

		};



		timer@17c90000 {

			#address-cells = <1>;

			#size-cells = <1>;
@@ -293,35 +323,5 @@ 
				status = "disabled";

			};

		};



		spmi_bus: spmi@c440000 {

			compatible = "qcom,spmi-pmic-arb";

			reg = <0xc440000 0x1100>,

			      <0xc600000 0x2000000>,

			      <0xe600000 0x100000>,

			      <0xe700000 0xa0000>,

			      <0xc40a000 0x26000>;

			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";

			interrupt-names = "periph_irq";

			interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;

			qcom,ee = <0>;

			qcom,channel = <0>;

			#address-cells = <2>;

			#size-cells = <0>;

			interrupt-controller;

			#interrupt-cells = <4>;

			cell-index = <0>;

		};



		tcsr_mutex_regs: syscon@1f40000 {

			compatible = "syscon";

			reg = <0x1f40000 0x40000>;

		};



		apss_shared: mailbox@17990000 {

			compatible = "qcom,sdm845-apss-shared";

			reg = <0x17990000 0x1000>;

			#mbox-cells = <1>;

		};

	};

};