Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 54939ea0 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Switch to use HWS indices rather than addresses 



If we use the STORE_DATA_INDEX function we can use a fixed offset and
avoid having to lookup up the engine HWS address. A step closer to being
able to emit the final breadcrumb during request_add rather than later
in the submission interrupt handler.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: default avatarTvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190318095204.9913-9-chris@chris-wilson.co.uk
parent 7c120045

drivers/gpu/drm/i915/intel_guc_submission.c

+2 −1
Original line number Diff line number Diff line
@@ -583,7 +583,8 @@ static void inject_preempt_context(struct work_struct *work) 
		} else {

			cs = gen8_emit_ggtt_write(cs,

						  GUC_PREEMPT_FINISHED,

						  addr);

						  addr,

						  0);

			*cs++ = MI_NOOP;

			*cs++ = MI_NOOP;

		}

drivers/gpu/drm/i915/intel_lrc.c

+7 −10
Original line number Diff line number Diff line
@@ -173,12 +173,6 @@ static void execlists_init_reg_state(u32 *reg_state, 
				     struct intel_engine_cs *engine,

				     struct intel_ring *ring);



static inline u32 intel_hws_hangcheck_address(struct intel_engine_cs *engine)

{

	return (i915_ggtt_offset(engine->status_page.vma) +

		I915_GEM_HWS_HANGCHECK_ADDR);

}



static inline struct i915_priolist *to_priolist(struct rb_node *rb)

{

	return rb_entry(rb, struct i915_priolist, node);
@@ -2214,11 +2208,14 @@ static u32 *gen8_emit_fini_breadcrumb(struct i915_request *request, u32 *cs) 
{

	cs = gen8_emit_ggtt_write(cs,

				  request->fence.seqno,

				  request->timeline->hwsp_offset);

				  request->timeline->hwsp_offset,

				  0);



	cs = gen8_emit_ggtt_write(cs,

				  intel_engine_next_hangcheck_seqno(request->engine),

				  intel_hws_hangcheck_address(request->engine));

				  I915_GEM_HWS_HANGCHECK_ADDR,

				  MI_FLUSH_DW_STORE_INDEX);





	*cs++ = MI_USER_INTERRUPT;

	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
@@ -2242,8 +2239,8 @@ static u32 *gen8_emit_fini_breadcrumb_rcs(struct i915_request *request, u32 *cs) 


	cs = gen8_emit_ggtt_write_rcs(cs,

				      intel_engine_next_hangcheck_seqno(request->engine),

				      intel_hws_hangcheck_address(request->engine),

				      0);

				      I915_GEM_HWS_HANGCHECK_ADDR,

				      PIPE_CONTROL_STORE_DATA_INDEX);



	*cs++ = MI_USER_INTERRUPT;

	*cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;

drivers/gpu/drm/i915/intel_ringbuffer.c

+6 −10
Original line number Diff line number Diff line
@@ -43,12 +43,6 @@ 
 */

#define LEGACY_REQUEST_SIZE 200



static inline u32 hws_hangcheck_address(struct intel_engine_cs *engine)

{

	return (i915_ggtt_offset(engine->status_page.vma) +

		I915_GEM_HWS_HANGCHECK_ADDR);

}



unsigned int intel_ring_update_space(struct intel_ring *ring)

{

	unsigned int space;
@@ -317,8 +311,8 @@ static u32 *gen6_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) 
	*cs++ = rq->fence.seqno;



	*cs++ = GFX_OP_PIPE_CONTROL(4);

	*cs++ = PIPE_CONTROL_QW_WRITE;

	*cs++ = hws_hangcheck_address(rq->engine) | PIPE_CONTROL_GLOBAL_GTT;

	*cs++ = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_STORE_DATA_INDEX;

	*cs++ = I915_GEM_HWS_HANGCHECK_ADDR | PIPE_CONTROL_GLOBAL_GTT;

	*cs++ = intel_engine_next_hangcheck_seqno(rq->engine);



	*cs++ = MI_USER_INTERRUPT;
@@ -423,8 +417,10 @@ static u32 *gen7_rcs_emit_breadcrumb(struct i915_request *rq, u32 *cs) 
	*cs++ = rq->fence.seqno;



	*cs++ = GFX_OP_PIPE_CONTROL(4);

	*cs++ = PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_GLOBAL_GTT_IVB;

	*cs++ = hws_hangcheck_address(rq->engine);

	*cs++ = (PIPE_CONTROL_QW_WRITE |

		 PIPE_CONTROL_STORE_DATA_INDEX |

		 PIPE_CONTROL_GLOBAL_GTT_IVB);

	*cs++ = I915_GEM_HWS_HANGCHECK_ADDR;

	*cs++ = intel_engine_next_hangcheck_seqno(rq->engine);



	*cs++ = MI_USER_INTERRUPT;

drivers/gpu/drm/i915/intel_ringbuffer.h

+2 −2
Original line number Diff line number Diff line
@@ -408,14 +408,14 @@ gen8_emit_ggtt_write_rcs(u32 *cs, u32 value, u32 gtt_offset, u32 flags) 
}



static inline u32 *

gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset)

gen8_emit_ggtt_write(u32 *cs, u32 value, u32 gtt_offset, u32 flags)

{

	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */

	GEM_BUG_ON(gtt_offset & (1 << 5));

	/* Offset should be aligned to 8 bytes for both (QW/DW) write types */

	GEM_BUG_ON(!IS_ALIGNED(gtt_offset, 8));



	*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;

	*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW | flags;

	*cs++ = gtt_offset | MI_FLUSH_DW_USE_GTT;

	*cs++ = 0;

	*cs++ = value;