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Commit 54397d85 authored by Ezequiel Garcia's avatar Ezequiel Garcia Committed by Jason Cooper
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ARM: kirkwood: Relocate PCIe device tree nodes 



Now that mbus has been added to the device tree, it's possible to
move the PCIe nodes out of the ocp node, placing it directly
below the mbus. This is a more accurate representation of the hardware.

Moving the PCIe nodes, we now need to introduce an extra cell to
encode the window target ID and attribute. Since this depends on
the PCIe port, we split the ranges translation entries, to
correspond to each MBus window.

In addition, we encode the PCIe memory and I/O apertures in the MBus
node, according to the MBus DT binding specification. The choice made
is 0xe0000000-0xf0000000 for memory space, and 0xf200000-0xf2100000 for
I/O space. These apertures can be changed in each per-board DT file.

Signed-off-by: default avatarEzequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: default avatarAndrew Lunn <andrew@lunn.ch>
Tested-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>
parent 3ec81e7e

arch/arm/boot/dts/kirkwood-6281.dtsi

+35 −31
Original line number Diff line number Diff line 
/ {

	mbus {

		pcie-controller {

			compatible = "marvell,kirkwood-pcie";

			status = "disabled";

			device_type = "pci";



			#address-cells = <3>;

			#size-cells = <2>;



			bus-range = <0x00 0xff>;



			ranges =

			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000

				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */

				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */>;



			pcie@1,0 {

				device_type = "pci";

				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;

				reg = <0x0800 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0

					  0x81000000 0 0 0x81000000 0x1 0 1 0>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &intc 9>;

				marvell,pcie-port = <0>;

				marvell,pcie-lane = <0>;

				clocks = <&gate_clk 2>;

				status = "disabled";

			};

		};

	};



	ocp@f1000000 {

		pinctrl: pinctrl@10000 {

			compatible = "marvell,88f6281-pinctrl";
@@ -41,37 +76,6 @@ 
			};

		};



		pcie-controller {

			compatible = "marvell,kirkwood-pcie";

			status = "disabled";

			device_type = "pci";



			#address-cells = <3>;

			#size-cells = <2>;



			bus-range = <0x00 0xff>;



			ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */

				  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */

			          0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */



			pcie@1,0 {

				device_type = "pci";

				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;

				reg = <0x0800 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

				ranges;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &intc 9>;

				marvell,pcie-port = <0>;

				marvell,pcie-lane = <0>;

				clocks = <&gate_clk 2>;

				status = "disabled";

			};

		};



		rtc@10300 {

			compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";

			reg = <0x10300 0x20>;

arch/arm/boot/dts/kirkwood-6282.dtsi

+55 −47
Original line number Diff line number Diff line 
/ {

	mbus {

		pcie-controller {

			compatible = "marvell,kirkwood-pcie";

			status = "disabled";

			device_type = "pci";



			#address-cells = <3>;

			#size-cells = <2>;



			bus-range = <0x00 0xff>;



			ranges =

			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000

			        0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000

				0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000

				0x82000000 0x1 0     MBUS_ID(0x04, 0xe8) 0       1 0 /* Port 0.0 MEM */

				0x81000000 0x1 0     MBUS_ID(0x04, 0xe0) 0       1 0 /* Port 0.0 IO  */

				0x82000000 0x2 0     MBUS_ID(0x04, 0xd8) 0       1 0 /* Port 1.0 MEM */

				0x81000000 0x2 0     MBUS_ID(0x04, 0xd0) 0       1 0 /* Port 1.0 IO  */>;



			pcie@1,0 {

				device_type = "pci";

				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;

				reg = <0x0800 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0

					  0x81000000 0 0 0x81000000 0x1 0 1 0>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &intc 9>;

				marvell,pcie-port = <0>;

				marvell,pcie-lane = <0>;

				clocks = <&gate_clk 2>;

				status = "disabled";

			};



			pcie@2,0 {

				device_type = "pci";

				assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;

				reg = <0x1000 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0

					  0x81000000 0 0 0x81000000 0x2 0 1 0>;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &intc 10>;

				marvell,pcie-port = <1>;

				marvell,pcie-lane = <0>;

				clocks = <&gate_clk 18>;

				status = "disabled";

			};

		};

	};

	ocp@f1000000 {



		pinctrl: pinctrl@10000 {
@@ -94,52 +149,5 @@ 
			status = "disabled";

		};



		pcie-controller {

			compatible = "marvell,kirkwood-pcie";

			status = "disabled";

			device_type = "pci";



			#address-cells = <3>;

			#size-cells = <2>;



			bus-range = <0x00 0xff>;



			ranges = <0x82000000 0 0x00040000 0x00040000 0 0x00002000   /* Port 0.0 registers */

			          0x82000000 0 0x00044000 0x00044000 0 0x00002000   /* Port 1.0 registers */

				  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */

			          0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */



			pcie@1,0 {

				device_type = "pci";

				assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;

				reg = <0x0800 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

				ranges;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &intc 9>;

				marvell,pcie-port = <0>;

				marvell,pcie-lane = <0>;

				clocks = <&gate_clk 2>;

				status = "disabled";

			};



			pcie@2,0 {

				device_type = "pci";

				assigned-addresses = <0x82001000 0 0x00044000 0 0x2000>;

				reg = <0x1000 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

				ranges;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &intc 10>;

				marvell,pcie-port = <1>;

				marvell,pcie-lane = <0>;

				clocks = <&gate_clk 18>;

				status = "disabled";

			};

		};

	};

};

arch/arm/boot/dts/kirkwood-db-88f6281.dts

+2 −1
Original line number Diff line number Diff line
@@ -18,7 +18,8 @@ 
	model = "Marvell DB-88F6281-BP Development Board";

	compatible = "marvell,db-88f6281-bp", "marvell,kirkwood-88f6281", "marvell,kirkwood";



	ocp@f1000000 {

	mbus {

		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;

		pcie-controller {

			status = "okay";

arch/arm/boot/dts/kirkwood-db-88f6282.dts

+2 −1
Original line number Diff line number Diff line
@@ -18,7 +18,8 @@ 
	model = "Marvell DB-88F6282-BP Development Board";

	compatible = "marvell,db-88f6282-bp", "marvell,kirkwood-88f6282", "marvell,kirkwood";



	ocp@f1000000 {

	mbus {

		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000>;

		pcie-controller {

			status = "okay";

arch/arm/boot/dts/kirkwood-db.dtsi

+0 −8
Original line number Diff line number Diff line
@@ -77,13 +77,5 @@ 
			cd-gpios = <&gpio1 6 0>;

			status = "okay";

		};



		pcie-controller {

			status = "okay";



			pcie@1,0 {

				status = "okay";

			};

		};

	};

};