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Commit 542622da authored by Olaf Dabrunz's avatar Olaf Dabrunz Committed by Ingo Molnar
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PCI quirks: disable AMD/ATI legacy boot interrupt generation 



Add quirks for several AMD/ATI chipsets to prevent generation of legacy boot
interrupts.

Integrates a separate older quirk to make IO-APIC mode work on
AMD 8131 rev. A0 and B0, which was due to an AMD erratum.

Signed-off-by: default avatarOlaf Dabrunz <od@suse.de>
Signed-off-by: default avatarStefan Assmann <sassmann@suse.de>
Cc: Jon Masters <jonathan@jonmasters.org>
Cc: Olaf Dabrunz <od@suse.de>
Cc: Stefan Assmann <sassmann@suse.de>
Cc: Ihno Krumreich <ihno@suse.de>
Cc: Sven Dietrich <sdietrich@suse.de>
Cc: Daniel Gollub <dgollub@suse.de>
Cc: Felix Foerster <ffoerster@suse.de>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 77251188

drivers/pci/quirks.c

+50 −21
Original line number Diff line number Diff line
@@ -602,27 +602,6 @@ static void __init quirk_ioapic_rmw(struct pci_dev *dev) 
		sis_apic_bug = 1;

}

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI,	PCI_ANY_ID,			quirk_ioapic_rmw);



#define AMD8131_revA0        0x01

#define AMD8131_revB0        0x11

#define AMD8131_MISC         0x40

#define AMD8131_NIOAMODE_BIT 0

static void quirk_amd_8131_ioapic(struct pci_dev *dev)

{ 

        unsigned char tmp;

        

        if (nr_ioapics == 0) 

                return;



        if (dev->revision == AMD8131_revA0 || dev->revision == AMD8131_revB0) {

                dev_info(&dev->dev, "Fixing up AMD8131 IOAPIC mode\n");

                pci_read_config_byte( dev, AMD8131_MISC, &tmp);

                tmp &= ~(1 << AMD8131_NIOAMODE_BIT);

                pci_write_config_byte( dev, AMD8131_MISC, tmp);

        }

} 

DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);

DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_ioapic);

#endif /* CONFIG_X86_IO_APIC */



/*
@@ -1449,6 +1428,56 @@ static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 
			"0x%04x:0x%04x\n", dev->vendor, dev->device);

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS,   PCI_DEVICE_ID_SERVERWORKS_HT1000SB, 	quirk_disable_broadcom_boot_interrupt);



/*

 * disable boot interrupts on AMD and ATI chipsets

 */

/*

 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131

 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode

 * (due to an erratum).

 */

#define AMD_813X_MISC			0x40

#define AMD_813X_NOIOAMODE		(1<<0)



static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)

{

	u32 pci_config_dword;



	if (noioapicquirk)

		return;



	pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);

	pci_config_dword &= ~AMD_813X_NOIOAMODE;

	pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);



	printk(KERN_INFO "disabled boot interrupts on PCI device "

			"0x%04x:0x%04x\n", dev->vendor, dev->device);

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8131_BRIDGE, 	quirk_disable_amd_813x_boot_interrupt);

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8132_BRIDGE, 	quirk_disable_amd_813x_boot_interrupt);



#define AMD_8111_PCI_IRQ_ROUTING	0x56



static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)

{

	u16 pci_config_word;



	if (noioapicquirk)

		return;



	pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);

	if (!pci_config_word) {

		printk(KERN_INFO "boot interrupts on PCI device 0x%04x:0x%04x "

				"already disabled\n",

				dev->vendor, dev->device);

		return;

	}

	pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);

	printk(KERN_INFO "disabled boot interrupts on PCI device "

			"0x%04x:0x%04x\n", dev->vendor, dev->device);

}

DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD,   PCI_DEVICE_ID_AMD_8111_SMBUS, 	quirk_disable_amd_8111_boot_interrupt);

#endif /* CONFIG_X86_IO_APIC */



/*